原创 PIC18F452看门狗例子

/* 
 * File:   MAIN.c
 * Author: Administrator
 *
 * Created on May 24, 2024, 10:32 AM
 */

#include 

//?????
 //CONFIG1L
#pragma config OSC = XT          // VREG Sleep Enable bit (Ultra low-power regulator is Disabled (Controlled by REGSLP bit)),?????????
#pragma config OSCS = OFF     // LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep),???? LF-INTOSC ???????
#pragma config PWRT = OFF         // SOSC Power Selection and mode Configuration bits (Digital (SCLKI) mode),SOSC ??????????,?? ? SCLKI?????? RC0 ? RC1 ? I/O ????
#pragma config BOR = ON           // Extended Instruction Set (Disabled)???????????????????????? ??????

// CONFIG1H
//#pragma config BORV = 20            // Oscillator (HS oscillator (Medium power, 4 MHz - 16 MHz))?HS????????
#pragma config WDT = ON           // PLL x4 Enable bit (Enabled),??PLL???????4?????32MHz
#pragma config WDTPS = 128           // Fail-Safe Clock Monitor (Disabled)????????????
#pragma config CCP2MUX = ON            // Internal External Oscillator Switch Over Mode (Disabled)???????

// CONFIG2L
#pragma config STVR = ON         // Power Up Timer (Disabled)??????????
#pragma config LVP = ON      // Brown Out Detect (Enabled in hardware, SBOREN disabled)????????????
#pragma config BORV = 3             // Brown-out Reset Voltage bits (1.8V)??????????1.8v
#pragma config CP0 = OFF     // BORMV Power level (ZPBORMV instead of BORMV is selected)???ZPBORMV???BORMV

// CONFIG2H
#pragma config CP1 = OFF      // Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled),???????
//#pragma config WDTEN = SWDTDIS      // Watchdog Timer (WDT enabled in hardware; SWDTEN bit disabled),?????WDT???SWDTEN?
#pragma config CP2 = OFF         // Watchdog Postscaler (1:256)???????1:256?????1.024s

// CONFIG3H
#pragma config CP3 = OFF    // ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)?1 = CANTX ? CANRX ?????? RB2 ? RB3 ?
#pragma config CPB = OFF   // MSSP address masking (7 Bit address masking mode)?1 = ?? 7 ???????
#pragma config CPD = OFF      // Master Clear Enable (MCLR Enabled, RE3 Disabled)???MCLR????

// CONFIG4L


// CONFIG6L
#pragma config WRT0 = OFF       // Table Write Protect 00800-01FFF (Disabled)?????
#pragma config WRT1 = OFF       // Table Write Protect 02000-03FFF (Disabled)?????
#pragma config WRT2 = OFF       // Table Write Protect 04000-05FFF (Disabled)?????
#pragma config WRT3 = OFF       // Table Write Protect 06000-07FFF (Disabled)?????

// CONFIG6H
#pragma config WRTC = OFF       // Config. Write Protect (Disabled)???????????
#pragma config WRTB = OFF       // Table Write Protect Boot (Disabled)?????????
#pragma config WRTD = OFF       // Data EE Write Protect (Disabled)???EEPROM?????

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protect 00800-01FFF (Disabled)??????
#pragma config EBTR1 = OFF      // Table Read Protect 02000-03FFF (Disabled)??????
#pragma config EBTR2 = OFF      // Table Read Protect 04000-05FFF (Disabled)??????
#pragma config EBTR3 = OFF      // Table Read Protect 06000-07FFF (Disabled)??????

// CONFIG7H
#pragma config EBTRB = OFF      // Table Read Protect Boot (Disabled)?????????

//void TMR1_ISR(void);
//void delay(void);
unsigned char j,flag;
unsigned char n;
//#pragma interrupt chk_isr
unsigned    long    i;
//#pragma code    My_Hiprio_Int=0x08
void delay(char);
//#pragma code
int main(int argc, char** argv) {
    PORTD=0;
    TRISD=0;
    TRISC=0;
    
    //T1CON=0X06;
    PORTD=0x01;
    INTCONbits.TMR0IF=0;
    T0CON=0X8F;
    PORTC=4;
    delay(100);
    PORTC=0;
    flag=0;
    while(1)
    {
        delay(1);
        flag++;
        PORTD=flag;
        //Nop();
        
    }
    return (0);
}
void    delay(char count)
{
    //ClrWdt();
    for(;count>0;count--)
    {
        INTCONbits.TMR0IF=0;
        TMR0H=0xf0;
        TMR0L=0X21;
        T0CONbits.TMR0ON=1;
        while(INTCONbits.TMR0IF==0);

    }
}