原创 带异步高电平有效的置/复位端的D触发器

module dff1( q, qb, d, clk, set, reset );
input d, clk, set, reset;
output q, qb;
//声明q和qb为reg类型,因为它需要在always块内赋值
reg q, qb;

always @( posedge clk or posedge set or posedge reset )
begin
if(reset)
begin
q <= 0;
qb <= 1;
end 
else
if (set)
begin
q <= 1;
qb <= 0;
end
else
begin
q <= d;
qb <= ~d;
end
end
endmodule

`timescale 1 ns/ 100 ps
module dff1_vlg_tst();
// constants                                           
// general purpose registers

// test vector input registers
reg clk;
reg d;
reg reset;
reg set;
// wires                                               
wire q;
wire qb;

// assign statements (if any)                          
dff1 i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.d(d),
	.q(q),
	.qb(qb),
	.reset(reset),
	.set(set)
);

always #5 clk=~clk;

initial 
begin
clk=0;
reset=0;
#10 reset=1;
#10 reset=0;
#10 set=1;

#10 set=0;
d=1;
#10 set=1;
#10 set=0;
d=0;
#10 set=1;
#10 set=0;
d=1;
#10 set=1;

#10 set=0;
d=0;
#10 $stop;
end                                          
endmodule
f仿真效果图

从图中看出，reset拉高，q=0,qb=1;
从图中看出，set拉高，q=1,qb=0;

从图中看出：set拉低，d=1,q=1,qb=0;

从图中看出，set=0;d=0,q=0,qb=1;

从图中看出，set拉高，q=1.qb=0;

从图中看出：set=0,d=1,q=1,qb=0