原创 11. Multicycle Paths Constraints实例I(Timing Constraints in Vi

2017-1-11 11:44 973 10 10

本节通过实例介绍一下多时钟周期路径(multicycle paths)的约束方法。


如图1中结构,主时钟fast_clk,时钟频率250MHz;时钟使能信号div_by_two,由主时钟2分频得到,作为寄存器的clock enable信号。




图1


HDL代码如下所示:


以下是代码片段:

module top(

fast_clk,

din_a,

din_b,

din_x,

din_y,

ab_out,

xy_out

);


////////////// PORT /////////////////////////////

input fast_clk;

input [7:0] din_a;

input [7:0] din_b;

input [7:0] din_x;

input [7:0] din_y;

output reg [15:0] ab_out;

output reg [15:0] xy_out;


////////////// ARCHITECTURE /////////////////////

// Clock Enable

reg div_by_two;

always@(posedge fast_clk)

div_by_two<=~div_by_two;


// Input Registers

reg [7:0] din_a_rg;

reg [7:0] din_b_rg;

reg [7:0] din_x_rg;

reg [7:0] din_y_rg;

always@(posedge fast_clk) begin

if(div_by_two) begin

din_a_rg <= din_a;

din_b_rg <= din_b;

din_x_rg <= din_x;

din_y_rg <= din_y;

end

end


// Multiplexer

wire [7:0] mult_a;

wire [7:0] mult_b;

assign mult_a = div_by_two ? din_a : din_x;

assign mult_b = div_by_two ? din_b : din_y;


// Multiplier

wire [15:0] mult_rlt;

assign mult_rlt = mult_a * mult_b;


// Ouptut Select

always@(posedge fast_clk) begin

if(div_by_two)

xy_out <= mult_rlt;

else

ab_out <= mult_rlt;

end


endmodule





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