原创 FPGA读写2PORTRAM过程分析1

if(!oPA0)

         begin

                                     data_wr<='h0;//写数据初始化

                                     ioRDY1_SLWRn<='b1;

                                     ioRDY0_SLRDn<='b1;

                                     oPA2_SLOEn<='b1;

                                     oPA4_FIFO0<='b1;

                                     oPA5_FIFO1<='b1;

                                     oe<='b0;

                                     FFlagA<='b0;

                                     sram_d<='h0;

                                     data_wr<='h0;         

                                     sram_a_i<='h1fff;

                                     sram_a_o<='h1fff;

                                     sram_rden<='b0;

                                     sram_wren<='b0;

                                     wr_flag<='b0;

                                     datacnt<='h1fff;

                                     STATE<=IDLE;

         End

OPA0 可以设置为中断输入，信号为电平或者下降沿，从程序看来是低电平触发。

ioRDY1_SLWRn<='b1;           pin4 output          写SLAVEFIFO 信号

ioRDY0_SLRDn<='b1;           pin5 output          读信号

oPA2_SLOEn<='b1;             pin45                输出使能信号

oPA4_FIFO0<='b1;

oPA5_FIFO1<='b1;