原创 如何用ultraedit高亮语法显示verilog

在wim7下安装了ultraedit，用来编辑verilog时看上去都是灰灰的，于是google了一下，发现只要把一段模板放在wordfile文件里就可以了，但是把模板代码放入ultraedit下安装目录中的 wordfilet中后打开verilog还是没有语法高亮显示。于是自己看了下configuration里面的设置，果然被我发现在syntax highlighting 里面有设置wordlist文件的路径，根本不是安装路径下的那个wordfile，把模板代码放入正确的文件果然有语法高亮了。打开ultraedit，查看高级/配置/编辑器显示/语法高亮，就可以看到正确目录了。还要注意的是，wim7 下C盘的appdata文件夹默认隐藏的，所以直接搜索C:\Users\asus\AppData就可以找到。QQ截图未命名.png

下面贴一下模板代码，放入wordfile的最后面就可以了，中第一行L后面的数字代表序号，要保证新添加的值是最大的，比如上一个L后面是13，那你添加的就写成14，如果以后还有新的格式就写成15，如此类推。wordfile里的文件都是.uew文件。

/L14″Verilog 1364-2001″ Line Comment = // Block Comment On = /* Block Comment Off = */ String Chars = ” File Extensions = V VL VMD
/Delimiters = ~!@%^&*()-+=|\/{}[]:;”<> ,        .?#
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scalared showcancelled signed small specify specparam strength strong0 strong1 supply0 supply1
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$getpattern
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$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane
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** `
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`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive
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#
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