原创 multstyle Verilog HDL Synthesis Attribute

 2014-2-19 11:25  1964 11 11 分类: FPGA/CPLD 文集: FPGA

multstyle Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that specifies the implementation style for multiplication operations (*) in your HDL source. Using this attribute, you can control whether the Quartus II software should preferentially implement a multiplication operation in general logic or dedicated hardware, if available in the target device.

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_multstyle. This synthesis attribute behaves identically to the multstyle synthesis attribute.

To use the multstyle attribute in a Verilog Design File (.v), apply the attribute to a Module Declaration, a Variable Declaration, or a specific Binary Expression containing the * operator. The synthesis attribute must have a string value of "logic" or "dsp", indicating a preferred implementation in logic or in dedicated hardware, respectively.

Note: You can specify a multstyle of "dsp" for the Quartus II software to implement as multiplication in dedicated hardware if one operand is a constant and you are not multiplying by a power of 2. The final implementation depends on the availability of dedicated hardware in the target device.

When applied to a Module Declaration, the attribute specifies the default implementation style for all instances of the * operator in the module. For example, in the following code, the multstyle attribute directs the Quartus II software to implement all multiplications inside module foo in dedicated multiplication hardware.

(* multstyle = "dsp" *) module foo(...);           // Verilog 2001 attribute 
module foo(..) ;  // Embedded attribute

When applied to a Variable Declaration, the attribute specifies the implementation style to be used for a multiplication operator whose result is directly assigned to the variable. It overrides the multstyle attribute associated with the enclosing module, if present. For example, in the following code, the multstyle attribute attached to variable res directs the Quartus II software to implement the a * b in general logic rather than dedicated hardware.

wire [8:0] a, b;
(* multstyle = "logic" *) wire [17:0] res;              // Verilog 2001 attribute
// wire [17:0] res ; // Embedded attribute
assign res = a * b;  // Multiplication must be directly assigned to res

When applied directly to a Binary Expression containing the * operator, the multstyle attribute specifies the implementation style for that specific operator alone and overrides any multstyle attribute associated with target variable or enclosing module. For example, in the following code, the multstyle attribute indicates that a * b should be implemented in dedicated hardware.

wire [8:0] a, b;
wire [17:0] res;
assign res = a * (* multstyle = "dsp" *) b;

Note: You must use the Verilog 2001 attribute syntax to apply the multstyle attribute to a Binary Expression.

上述说明来自altera12.0的在线帮助文档.

经过实测,在altera中采用上述方法可行,如果指定multstyle为"logic"乘号仍然会被lpm_mult替换,但是在不会被映射为dsp单元,而是采用logic实现lpm_mult.

altera提供的其他方法:

1.set_global_assignment -name AUTO_DSP_REOCGNITION OFF/ON

根据altera在线文档,AUTO_DSP_RECOGNITION选项必须具体指到需要限定的模块,而采用set_instance_assignment 加上该选项后,仍然不能控制采用dsp还是逻辑实现乘法器.该方法行不通;

2.set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS",根据在线文档也需要指到具体模块,但是不起作用;如果全局使用该选项,会导致所有dsp均不使用,甚至加法树也被误杀;lpm_mult中明确指定采用dsp的也不能幸免.因此如果要精细的决定部分模块中的乘法器不用dsp实现也节省dsp资源,该选项不能达到目的.

fpga