always@(reg_cmd_idx)
begin
case(reg_cmd_idx)
0 : reg_cmd_data <= 24'h310311; // system clock from pad, bit[1]
1 : reg_cmd_data <= 24'h300882; // software reset, bit[7]// delay 5ms
2 : reg_cmd_data <= 24'hFFFF0A; //dealy
3 : reg_cmd_data <= 24'h303108; //bypass regulator
4 : reg_cmd_data <= 24'hFFFF0A; //dealy
5 : reg_cmd_data <= 24'h300842; // software power down, bit[6]
6 : reg_cmd_data <= 24'h310303; // system clock from PLL, bit[1]
7 : reg_cmd_data <= 24'h3017ff; // FREX, Vsync, HREF, PCLK, D[9 : 6] output enable
8 : reg_cmd_data <= 24'h3018ff; // D[5 : 0], GPIO[1 : 0] output enable
9 : reg_cmd_data <= 24'h30341A; // MIPI 10-bit
10 : reg_cmd_data <= 24'h303713; // PLL root divider, bit[4], PLL pre-divider, bit[3 : 0]
11 : reg_cmd_data <= 24'h310801; // PCLK root divider, bit[5 : 4], SCLK2x root divider, bit[3 : 2] // SCLK root divider, bit[1 : 0]
12 : reg_cmd_data <= 24'h363036;
13 : reg_cmd_data <= 24'h36310e;
14 : reg_cmd_data <= 24'h3632e2;
15 : reg_cmd_data <= 24'h363312;
16 : reg_cmd_data <= 24'h3621e0;
17 : reg_cmd_data <= 24'h3704a0;
18 : reg_cmd_data <= 24'h37035a;
19 : reg_cmd_data <= 24'h371578;
20 : reg_cmd_data <= 24'h371701;
21 : reg_cmd_data <= 24'h370b60;
22 : reg_cmd_data <= 24'h37051a;
23 : reg_cmd_data <= 24'h390502;
24 : reg_cmd_data <= 24'h390610;
25 : reg_cmd_data <= 24'h39010a;
26 : reg_cmd_data <= 24'h373112;
27 : reg_cmd_data <= 24'h360008; // VCM control
28 : reg_cmd_data <= 24'h360133; // VCM control
29 : reg_cmd_data <= 24'h302d60; // system control
30 : reg_cmd_data <= 24'h362052;
31 : reg_cmd_data <= 24'h371b20;
32 : reg_cmd_data <= 24'h471c50;
33 : reg_cmd_data <= 24'h3a1343; // pre-gain = 1.047x
34 : reg_cmd_data <= 24'h3a1800; // gain ceiling
35 : reg_cmd_data <= 24'h3a19f8; // gain ceiling = 15.5x
36 : reg_cmd_data <= 24'h363513;
37 : reg_cmd_data <= 24'h363603;
38 : reg_cmd_data <= 24'h363440;
39 : reg_cmd_data <= 24'h362201; // 50/60Hz detection 50/60Hz 灯光条纹过滤
40 : reg_cmd_data <= 24'h3c0134; // Band auto, bit[7]
41 : reg_cmd_data <= 24'h3c0428; // threshold low "sum "
42 : reg_cmd_data <= 24'h3c0598; // threshold high sum
43 : reg_cmd_data <= 24'h3c0600; // light meter 1 threshold[15 : 8]
44 : reg_cmd_data <= 24'h3c0708; // light meter 1 threshold[7 : 0]
45 : reg_cmd_data <= 24'h3c0800; // light meter 2 threshold[15 : 8]
46 : reg_cmd_data <= 24'h3c091c; // light meter 2 threshold[7 : 0]
47 : reg_cmd_data <= 24'h3c0a9c; // sample number[15 : 8]
48 : reg_cmd_data <= 24'h3c0b40; // sample number[7 : 0]
49 : reg_cmd_data <= 24'h381000; // Timing Hoffset[11 : 8] =(2592/2-960)/2
50 : reg_cmd_data <= 24'h3811A8; // Timing Hoffset[7 : 0]
51 : reg_cmd_data <= 24'h381200; // Timing Voffset[10 : 8]
52 : reg_cmd_data <= 24'h370864;
53 : reg_cmd_data <= 24'h400102; // BLC start from line 2
54 : reg_cmd_data <= 24'h40051a; // BLC always update
55 : reg_cmd_data <= 24'h300000; // enable blocks
56 : reg_cmd_data <= 24'h3004ff; // enable clocks
57: reg_cmd_data <= 24'h300e58; // MIPI power down, DVP enable
58: reg_cmd_data <= 24'h302e00;
//59 : reg_cmd_data <= 24'h430030; // YUV422
59 : reg_cmd_data <= 24'h430010; // Y8
60 : reg_cmd_data <= 24'h501f00; // ISP YUV
61 : reg_cmd_data <= 24'h440e00;
62 : reg_cmd_data <= 24'h5000a7; // Lenc on, raw gamma on, BPC on, WPC on, CIP on // AEC target 自动曝光控制
63 : reg_cmd_data <= 24'h3a0f30; // stable range in high
64 : reg_cmd_data <= 24'h3a1028; // stable range in low
65 : reg_cmd_data <= 24'h3a1b30; // stable range out high
66 : reg_cmd_data <= 24'h3a1e26; // stable range out low
67 : reg_cmd_data <= 24'h3a1160; // fast zone high
68 : reg_cmd_data <= 24'h3a1f14; // fast zone low// Lens correction for ? 镜头补偿
69 : reg_cmd_data <= 24'h580023;
70 : reg_cmd_data <= 24'h580114;
71 : reg_cmd_data <= 24'h58020f;
72 : reg_cmd_data <= 24'h58030f;
73 : reg_cmd_data <= 24'h580412;
74 : reg_cmd_data <= 24'h580526;
75 : reg_cmd_data <= 24'h58060c;
76 : reg_cmd_data <= 24'h580708;
77 : reg_cmd_data <= 24'h580805;
78 : reg_cmd_data <= 24'h580905;
79 : reg_cmd_data <= 24'h580a08;
80 : reg_cmd_data <= 24'h580b0d;
81 : reg_cmd_data <= 24'h580c08;
82 : reg_cmd_data <= 24'h580d03;
83 : reg_cmd_data <= 24'h580e00;
84 : reg_cmd_data <= 24'h580f00;
85 : reg_cmd_data <= 24'h581003;
86 : reg_cmd_data <= 24'h581109;
87 : reg_cmd_data <= 24'h581207;
88 : reg_cmd_data <= 24'h581303;
89 : reg_cmd_data <= 24'h581400;
90 : reg_cmd_data <= 24'h581501;
91 : reg_cmd_data <= 24'h581603;
92 : reg_cmd_data <= 24'h581708;
93 : reg_cmd_data <= 24'h58180d;
94 : reg_cmd_data <= 24'h581908;
95 : reg_cmd_data <= 24'h581a05;
96 : reg_cmd_data <= 24'h581b06;
97 : reg_cmd_data <= 24'h581c08;
98 : reg_cmd_data <= 24'h581d0e;
99 : reg_cmd_data <= 24'h581e29;
100: reg_cmd_data <= 24'h581f17;
101: reg_cmd_data <= 24'h582011;
102 : reg_cmd_data <= 24'h582111;
103 : reg_cmd_data <= 24'h582215;
104 : reg_cmd_data <= 24'h582328;
105 : reg_cmd_data <= 24'h582446;
106 : reg_cmd_data <= 24'h582526;
107 : reg_cmd_data <= 24'h582608;
108 : reg_cmd_data <= 24'h582726;
109 : reg_cmd_data <= 24'h582864;
110 : reg_cmd_data <= 24'h582926;
111 : reg_cmd_data <= 24'h582a24;
112 : reg_cmd_data <= 24'h582b22;
113 : reg_cmd_data <= 24'h582c24;
114 : reg_cmd_data <= 24'h582d24;
115 : reg_cmd_data <= 24'h582e06;
116 : reg_cmd_data <= 24'h582f22;
117 : reg_cmd_data <= 24'h583040;
118 : reg_cmd_data <= 24'h583142;
119 : reg_cmd_data <= 24'h583224;
120 : reg_cmd_data <= 24'h583326;
121 : reg_cmd_data <= 24'h583424;
122 : reg_cmd_data <= 24'h583522;
123 : reg_cmd_data <= 24'h583622;
124 : reg_cmd_data <= 24'h583726;
125 : reg_cmd_data <= 24'h583844;
126 : reg_cmd_data <= 24'h583924;
127 : reg_cmd_data <= 24'h583a26;
128 : reg_cmd_data <= 24'h583b28;
129 : reg_cmd_data <= 24'h583c42;
130 : reg_cmd_data <= 24'h583dce; // lenc BR offset // AWB 自动白平��?
131 : reg_cmd_data <= 24'h5180ff; // AWB B block
132 : reg_cmd_data <= 24'h5181f2; // AWB control
133 : reg_cmd_data <= 24'h518200; // [7 : 4] max local counter, [3 : 0] max fast counter
134 : reg_cmd_data <= 24'h518314; // AWB advanced
135 : reg_cmd_data <= 24'h518425;
136 : reg_cmd_data <= 24'h518524;
137 : reg_cmd_data <= 24'h518609;
138 : reg_cmd_data <= 24'h518709;
139 : reg_cmd_data <= 24'h518809;
140 : reg_cmd_data <= 24'h518975;
141 : reg_cmd_data <= 24'h518a54;
142 : reg_cmd_data <= 24'h518be0;
143 : reg_cmd_data <= 24'h518cb2;
144 : reg_cmd_data <= 24'h518d42;
145 : reg_cmd_data <= 24'h518e3d;
146 : reg_cmd_data <= 24'h518f56;
147 : reg_cmd_data <= 24'h519046;
148 : reg_cmd_data <= 24'h5191f8; // AWB top limit
149 : reg_cmd_data <= 24'h519204; // AWB bottom limit
150 : reg_cmd_data <= 24'h519370; // red limit
151 : reg_cmd_data <= 24'h5194f0; // green limit
152 : reg_cmd_data <= 24'h5195f0; // blue limit
153 : reg_cmd_data <= 24'h519603; // AWB control
154 : reg_cmd_data <= 24'h519701; // local limit
155 : reg_cmd_data <= 24'h519804;
156 : reg_cmd_data <= 24'h519912;
157 : reg_cmd_data <= 24'h519a04;
158 : reg_cmd_data <= 24'h519b00;
159 : reg_cmd_data <= 24'h519c06;
160 : reg_cmd_data <= 24'h519d82;
161 : reg_cmd_data <= 24'h519e38; // AWB control // Gamma 伽玛曲线
162 : reg_cmd_data <= 24'h548001; // Gamma bias plus on, bit[0]
163 : reg_cmd_data <= 24'h548108;
164 : reg_cmd_data <= 24'h548214;
165 : reg_cmd_data <= 24'h548328;
166 : reg_cmd_data <= 24'h548451;
167 : reg_cmd_data <= 24'h548565;
168 : reg_cmd_data <= 24'h548671;
169 : reg_cmd_data <= 24'h54877d;
170 : reg_cmd_data <= 24'h548887;
171 : reg_cmd_data <= 24'h548991;
172 : reg_cmd_data <= 24'h548a9a;
173 : reg_cmd_data <= 24'h548baa;
174 : reg_cmd_data <= 24'h548cb8;
175 : reg_cmd_data <= 24'h548dcd;
176 : reg_cmd_data <= 24'h548edd;
177 : reg_cmd_data <= 24'h548fea;
178 : reg_cmd_data <= 24'h54901d; // color matrix 色彩矩阵
179 : reg_cmd_data <= 24'h53811e; // CMX1 for Y
180 : reg_cmd_data <= 24'h53825b; // CMX2 for Y
181 : reg_cmd_data <= 24'h538308; // CMX3 for Y
182 : reg_cmd_data <= 24'h53840a; // CMX4 for U
183 : reg_cmd_data <= 24'h53857e; // CMX5 for U
184 : reg_cmd_data <= 24'h538688; // CMX6 for U
185 : reg_cmd_data <= 24'h53877c; // CMX7 for V
186 : reg_cmd_data <= 24'h53886c; // CMX8 for V
187 : reg_cmd_data <= 24'h538910; // CMX9 for V
188 : reg_cmd_data <= 24'h538a01; // sign[9]
189 : reg_cmd_data <= 24'h538b98; // sign[8 : 1] // UV adjust UV色彩饱和度调��?
190 : reg_cmd_data <= 24'h558006; // saturation on, bit[1]
191 : reg_cmd_data <= 24'h558340;
192 : reg_cmd_data <= 24'h558410;
193 : reg_cmd_data <= 24'h558910;
194 : reg_cmd_data <= 24'h558a00;
195 : reg_cmd_data <= 24'h558bf8;
196 : reg_cmd_data <= 24'h501d40; // enable manual offset of contrast// CIP 锐化和降��?
197 : reg_cmd_data <= 24'h530008; // CIP sharpen MT threshold 1
198 : reg_cmd_data <= 24'h530130; // CIP sharpen MT threshold 2
199 : reg_cmd_data <= 24'h530210; // CIP sharpen MT offset 1
200 : reg_cmd_data <= 24'h530300; // CIP sharpen MT offset 2
201 : reg_cmd_data <= 24'h530408; // CIP DNS threshold 1
202 : reg_cmd_data <= 24'h530530; // CIP DNS threshold 2
203 : reg_cmd_data <= 24'h530608; // CIP DNS offset 1
204 : reg_cmd_data <= 24'h530716; // CIP DNS offset 2
205 : reg_cmd_data <= 24'h530908; // CIP sharpen TH threshold 1
206 : reg_cmd_data <= 24'h530a30; // CIP sharpen TH threshold 2
207 : reg_cmd_data <= 24'h530b04; // CIP sharpen TH offset 1
208 : reg_cmd_data <= 24'h530c06; // CIP sharpen TH offset 2
209 : reg_cmd_data <= 24'h502500;
210 : reg_cmd_data <= 24'h474021; //VSYNC 高有效
211 : reg_cmd_data <= 24'h321203; //start group 3 //对比度+3
212 : reg_cmd_data <= 24'h55862c; //
213 : reg_cmd_data <= 24'h55851c; //
214 : reg_cmd_data <= 24'h321213; //end group 3
215 : reg_cmd_data <= 24'h3212a3; //launch group 3
//216 : reg_cmd_data <= 24'h300802; // wake up from standby, bit[6]
217 : reg_cmd_data <= 24'hFFFF05; //dealy
// 960x960, 60fps
// Input Clock = 24Mhz, PCLK = 84MHz
218 : reg_cmd_data <= 24'h303511; //PLL
219 : reg_cmd_data <= 24'h303669; //PLL
220 : reg_cmd_data <= 24'h3c0707; //lightmet er 1 threshold[7:0]
221 : reg_cmd_data <= 24'h382041; //flip
222 : reg_cmd_data <= 24'h382101; //mirror
223 : reg_cmd_data <= 24'h381431; //timing X inc
224 : reg_cmd_data <= 24'h381531; //timing Y inc
225 : reg_cmd_data <= 24'h380000; //HS
226 : reg_cmd_data <= 24'h380100; //HS
227 : reg_cmd_data <= 24'h380200; //VS
228 : reg_cmd_data <= 24'h380300; //VS
229 : reg_cmd_data <= 24'h38040a; //HW (HE),A3F->2623
230 : reg_cmd_data <= 24'h38053f; //HW (HE)
231 : reg_cmd_data <= 24'h380607; //VH (VE),79F->1951
232 : reg_cmd_data <= 24'h38079f; //VH (VE)
233 : reg_cmd_data <= 24'h380803; //DVPHO,3C0->960
234 : reg_cmd_data <= 24'h3809C0; //DVPHO
235 : reg_cmd_data <= 24'h380a03; //DVPVO
236 : reg_cmd_data <= 24'h380bC0; //DVPVO
237 : reg_cmd_data <= 24'h380c05; //HTS,5F8->1528
238 : reg_cmd_data <= 24'h380dF8; //HTS
239 : reg_cmd_data <= 24'h380e03; //VTS,3F0->1008
240 : reg_cmd_data <= 24'h380fF0; //VTS
241 : reg_cmd_data <= 24'h381308; //timing V offset
242 : reg_cmd_data <= 24'h361800;
243 : reg_cmd_data <= 24'h361229;
244 : reg_cmd_data <= 24'h370952;
245 : reg_cmd_data <= 24'h370c03;
246 : reg_cmd_data <= 24'h3a0202; //60Hz max exposure
247 : reg_cmd_data <= 24'h3a03e0; //60Hz max exposure
248 : reg_cmd_data <= 24'h3a1402; //50Hz max exposure
249 : reg_cmd_data <= 24'h3a15e0; //50Hz max exposure
250 : reg_cmd_data <= 24'h400402; //BLC line number
251 : reg_cmd_data <= 24'h30021c; //reset JFIFO, SFIFO, JPG
252 : reg_cmd_data <= 24'h3006c3; //disable clock of JPEG2x, JPEG
253 : reg_cmd_data <= 24'h471303; //JPEG mode 3
254 : reg_cmd_data <= 24'h440704; //Quantization scale
255 : reg_cmd_data <= 24'h460b37;
256 : reg_cmd_data <= 24'h460c20;
257 : reg_cmd_data <= 24'h483716; //MIPI global timing
258 : reg_cmd_data <= 24'h382404; //PCLK manual divider
259 : reg_cmd_data <= 24'h500100; //SDE off, CMX off, AWB off
260 : reg_cmd_data <= 24'h350303; //AEC/AGC off
261 : reg_cmd_data <= {16'h3500, 4'h0,4'h8}; //Bit[3:0]: Exposure [19:16]
262 : reg_cmd_data <= {16'h3501, 8'h00}; //Bit[7:0]: Exposure [15:8]
263 : reg_cmd_data <= {16'h3502, 4'h0, 4'h0}; //Bit[7:0]: Exposure [7:0]
264 : reg_cmd_data <= {16'h350A, 6'h0,2'h0}; //Bit[1:0]: Real gain[9:8]
265 : reg_cmd_data <= {16'h350B, 8'h00}; //Bit[7:0]: Real gain[7:0]
266 : reg_cmd_data <= 24'hFFFF0A; //dealy
267 : reg_cmd_data <= 24'h300802; // wake up from standby, bit[6]
default: reg_cmd_data <= 24'h000000; //pass;
endcase
end
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