原创 eda实验课---------频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity plj is
  port ( start:in std_logic;                     
       clk,clk1:in std_logic;
       y1,y2,y3,y4:out std_logic_vector(3 downto 0));               
 end plj;
architecture behav of PLj is
signal b1,b2,b3,b4: std_logic_vector(3 downto 0);
signal q :integer range 0 to 49999999;                 
signal en,bclk:std_logic;                             
begin
second:process(clk)                     
begin
  if start='1' then q<=0;
  elsif clk'event and clk='1' then
     if q<49999999 then q<=q+1;
     else q<=49999999;
     end if;
  end if;
  if q<49999999 and  start='0' then en<='1';
  else en<='0';
  end if;
end process;
and2:process(en,clk1)                  
begin
  bclk<=clk1 and en;
end process;
com:process(start,bclk)         
begin
  if start='1' then                            
b1<="0000";b2<="0000";b3<="0000";b4<="0000";
  elsif bclk'event and bclk='1' then 
     if b1="1001" then b1<="0000";                   
        if b2="1001" then b2<="0000";                
           if b3="1001" then b3<="0000";            
              if b4="1001" then b4<="0000";                          
              else b4<=b4+1;
              end if;
           else b3<=b3+1;
           end if;
        else b2<=b2+1;
        end if;
     else b1<=b1+1;
     end if;
  end if;
end process;

process(b1,b2,b3,b4)
begin 
if en = '0' then
y1 <= b1;
y2 <= b2;
y3 <= b3;
y4 <= b4;
end if;
end process;

end behav;