原创 基于VHDL语言来实现对ADC0809控制程序与仿真

基于VHDL语言来实现对ADC0809控制程序与仿真。<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

--文件名：ADC0809.vhd

--功能：基于VHDL语言来实现对ADC0809控制

--说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系

--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity ADC0809 is

  port (   d       : in std_logic_vector(7 downto 0);          --ADC0809输出的采样数据

         clk,eoc   : in std_logic;        --clk为系统时钟，eoc为ADC0809转换结束信号

clk1,start, ale,en: out std_logic;                                --ADC0809控制信号

        abc_in    :in std_logic_vector(2 downto 0);                     --模拟选通信号

abc_out     :out std_logic_vector(2 downto 0);        --ADC0809模拟信号选通信号

        q        : out std_logic_vector(7 downto 0));          --送至8个并排数码管信号

 end ADC0809;

architecture behav of ADC0809 is

type states is ( st0,st1, st2, st3, st4,st5,st6);                         --定义各状态的子类型

signal current_state, next_state:states:=st0;

signal regl :std_logic_vector(7 downto 0);                            --中间数据寄存信号

signal qq:std_logic_vector(7 downto 0);

begin

com:process(current_state,eoc)                             --规定各种状态的转换方式

begin

  case current_state is

  when st0=>next_state<=st1;ale<='0';start<='0';en<='0';

  when st1=>next_state<=st2;ale<='1';start<='0';en<='0';

  when st2=>next_state<=st3;ale<='0';start<='1';en<='0';

  when st3=>             ale<='0';start<='0';en<='0';

        if eoc='1' then next_state<=st3;                            --检测EOC的下降沿

        else next_state<=st4;

        end if;   

  when st4=>              ale<='0';start<='0';en<='0';

        if eoc='0' then next_state<=st4;                            --检测EOC的上升沿

else next_state<=st5;

end if;

  when st5=>next_state<=st6;ale<='0';start<='0';en<='1';

  when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;

  when others=> next_state<=st0;ale<='0';start<='0';en<='0';

  end case;

end process;

clock:process(clk)                 --对系统时钟进行分频，得到ADC0809转换工作时钟

begin

 if clk'event and clk='1' then qq<=qq+1;              --在clk1的上升沿，转换至下一状态

if QQ="01111111" THEN clk1<='1'; current_state <=next_state;   

  elsif qq<="01111111" then clk1<='0';    

    end if; 

end if;

end process;

q<=regl;  abc_out<=abc_in; 

end behav;