原创 LED动态扫描verilog代码

//************************************************************
//LED动态扫描verilog 代码，D1~8为数码管输入
//2007.07.26 By levension @SCUT
//************************************************************
module LED(clk,segout,bitout,D1,D2,D3,D4,D5,D6,D7,D8);

input clk;
input [3:0] D1,D2,D3,D4,D5,D6,D7,D8;
output [3:0] segout;
output [7:0] bitout;

reg [3:0] segout;
reg [7:0] bitout;

parameter S0=3'd0,            //采用状态机的方法
          S1=3'd1,
    S2=3'd2,
    S3=3'd3,
    S4=3'd4,
    S5=3'd5,
    S6=3'd6,
    S7=3'd7;

reg [2:0] state;
 
always @(posedge clk)
 begin
 case(state)
    S0:                                    //第1个数码管
  begin
  segout <=D1;
  bitout <=8'b0000_0001;
  state=S1;
  end
    S1:                                  //第2个数码管
  begin
  segout <=D2;
  bitout <=8'b0000_0010;
  state=S2;
  end
    S2:                                  //第3个数码管
  begin
  segout <=D3;
  bitout <=8'b0000_0100;
  state=S3;
  end
    S3:                                  //第4个数码管
  begin
  segout <=D4;
  bitout <=8'b0000_1000;
  state=S4;
  end
    S4:                                  //第5个数码管
  begin
  segout <=D5;
  bitout <=8'b0001_0000;
  state=S5;
  end
    S5:                                   //第6个数码管
  begin
  segout <=D6;
  bitout <=8'b0010_0000;
  state=S6;
  end
    S6:                                     //第7个数码管
  begin
  segout <=D7;
  bitout <=8'b0100_0000;
  state=S7;
  end
    S7:                                    //第8个数码管
  begin
  segout <=D8;
  bitout <=8'b1000_0000;
  state=S0;
  end
 endcase
 end
endmodule