原创 数字钟VerilogHDL代码

// *********************************************************************
// 数字钟VerilogHDL代码
//2007.7.27 by Levension @SCUT

//参考网上范例修改的
// *********************************************************************

module clock_main(clk_4Hz,mode,sel,add,alert,hour,min,sec,msec,LD);

input clk_4Hz;
input mode,sel,add;
output alert;
output [7:0] hour,min,sec,msec;
output [2:0] LD;

reg[7:0] hour,min,sec,msec,thour,tmin,tsec,ahour,amin,asec;
reg ath,atm,ats,aah,aam,aas;

reg [2:0]LD;

reg clk_1Hz,start,m_clk,h_clk;
reg [1:0] cnt,Nmode,Bsel;

wire ct1,ct2,ct3,cta,ctb,ctc;

parameter TIMER="2"'b00,
    SETTM="2"'b01,
    ALERT="2"'b10;

always @(posedge clk_4Hz)   //产生1Hz
   begin
   cnt<=cnt==3?0:cnt+1;
   if(cnt<2) clk_1Hz=0;
     else    clk_1Hz=1;
   end

always @(negedge mode)      //模式选择
  begin
  if(Nmode==2'd2) Nmode<=2'd0;
  else Nmode<=Nmode+1;
  end

always
  case(Nmode)                //发光二极管指示模式
   TIMER:LD<=3'b110;
    SETTM:LD<=3'b101;
    ALERT:LD<=3'b011;
  endcase

always @(negedge sel)         //调整位置选择 
  if(Nmode==SETTM||Nmode==ALERT)
       begin
       if(Bsel==2'd2) Bsel<=2'd0;
       else Bsel<=Bsel+1;
       end

always                       //add调整信号
begin
 case(Nmode)
 SETTM:                       //设置时间
  begin
   case(Bsel)
    2'd0:ath <=~add;
    2'd1:atm <=~add;
    2'd2:ats <=~add;
    endcase
   {aah,aam,aas}<=0;
  end
 ALERT:                         //设置闹鳞
  begin
  case(Bsel)
   2'd0:aah <=~add;
   2'd1:aam <=~add;
   2'd2:aas <=~add;
  endcase
  {ath,atm,ats} <=0;
  end
 default:
  {aah,aam,aas,ath,atm,ats}<=0;
 endcase
end

assign ct1=(ats&clk_4Hz)|(!ats&clk_1Hz); //ct1 用于计时、校时中的秒计数
assign ct2=(atm&clk_4Hz)|(!atm&m_clk);  //ct2 用于计时、校时中的分计数
assign ct3=(ath&clk_4Hz)|(!ath&h_clk);  //ct3用于计时、校时中的时计数

assign cta=(aas&clk_4Hz);              //cta用于闹铃秒计数
assign ctb=(aam&clk_4Hz);              //ctb用于闹铃分计数
assign ctc=(aah&clk_4Hz);             //ctc用于闹铃时计数

always @(posedge ct1)                  //秒计时和秒调整进程
begin
 if(tsec==8'h59)
    begin
    tsec<=0;
    m_clk<=1;
    end
 else
 begin
 if(tsec[3:0]==4'b1001)
   begin
   tsec[3:0]<=4'b0000;
   tsec[7:4]<=tsec[7:4]+1;
   end
 else tsec[3:0]<=tsec[3:0]+1;
    m_clk<=0;
 end
end

always @(posedge ct2) //分计时和分调整进程
begin
 if(tmin==8'h59)
  begin
  tmin <=0;
  h_clk <=1;
  end
  else
  begin
  if(tmin[3:0]==9)
  begin
  tmin[3:0]<=0;
  tmin[7:4]<=tmin[7:4]+1;
  end
  else tmin[3:0]<=tmin[3:0]+1;
  h_clk<=0;
  end
end

always @(posedge ct3)   //小时计时和小时调整进程
if(thour==8'h23) thour<=0;
else if(thour[3:0]==9)
begin
thour[7:4]<=thour[7:4]+1;
thour[3:0]<=0;
end
else thour[3:0]<=thour[3:0]+1;

always @(posedge cta)       //闹铃秒调整进程
begin
 if(asec==8'h59)
    asec<=0;
 else
 begin
 if(asec[3:0]==4'b1001)
   begin
   asec[3:0]<=4'b0000;
   asec[7:4]<=asec[7:4]+1;
   end
  else asec[3:0]<=asec[3:0]+1;
 end
end

always @(posedge ctb)        //闹铃分调整进程
begin
 if(amin==8'h59)
  amin <=0;
  else
  begin
  if(amin[3:0]==9)
  begin
  amin[3:0]<=0;
  amin[7:4]<=amin[7:4]+1;
  end
  else amin[3:0]<=amin[3:0]+1;
  end
end

always @(posedge ctc)                    //闹铃时调整进程
if(ahour==8'h23) ahour<=0;
else if(ahour[3:0]==9)
begin
ahour[7:4]<=ahour[7:4]+1;
ahour[3:0]<=0;
end
else ahour[3:0]<=ahour[3:0]+1;

assign alert=((ahour==thour)&&(amin==tmin)&&(Nmode==TIMER))?1:0;   //闹铃功能

always   //显示控制
case(Nmode)
TIMER: begin hour<=thour; min<=tmin; sec<=tsec; msec<=0; end
SETTM: begin hour<=thour; min<=tmin; sec<=tsec; msec<=0; end
ALERT: begin hour<=ahour; min<=amin; sec<=asec; msec<=0; end
endcase

endmodule