原创 VHDL按键去抖

 2009-3-28 20:28  6601 8 8 分类: FPGA/CPLD

按键检测需要消抖，一般有硬件和软件两种方式。硬件就是加去抖动电路，这样从根本上解决按键抖动问题。除了用专用电路以外，用可编程FPGA或者CPLD设计相应的逻辑和时序电路，对按键信号进行处理，同样可以达到去抖动的目的。

本例中用状态机实现了消抖电路：

端口描述：clk 输入检测时钟；reset 复位信号；din 原始按键信号输入； dout 去抖动输出信号。

VHDL源码如下：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY xiaod IS
PORT
(
   clk      : IN STD_LOGIC ;
   reset   : IN STD_LOGIC ;
   din    : IN STD_LOGIC ;
   dout   : OUT STD_LOGIC
);
END ENTITY;

ARCHITECTURE RTL OF xiaod IS
TYPE state IS( s0,s1,s2,s3);
SIGNAL pre_s, next_s: state;

BEGIN

P0:PROCESS( reset, clk )
BEGIN
   if reset = '0' then
    pre_s <= s0;
   elsif rising_edge( clk ) then
    pre_s <= next_s;
   else
    null;
   end if;
END PROCESS P0;

P1:PROCESS( pre_s, next_s, din )
BEGIN
   case pre_s is

    when s0 =>
     dout <= '1';
     if din = '1' then
      next_s <= s0;
     else
      next_s <= s1;
     end if;

    when s1 =>
     dout <= '1';
     if din = '1' then
      next_s <= s0;
     else
      next_s <= s2;
     end if;

    when s2 =>
     dout <= '1';
     if din = '1' then
      next_s <= s0;
     else
      next_s <= s3;
     end if;

    when s3 =>
     dout <= '0';
     if din = '1' then
      next_s <= s0;
     else
      next_s <= s1;
     end if;
   end case;

END PROCESS P1;

END RTL;

多按键去抖动电路VHDL源码，按键个数参数化，每个按键处理调用了上面的模块：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY Nxiaod IS
GENERIC( width: positive:= 5 );

PORT
(
   clk      : IN STD_LOGIC ;
   reset   : IN STD_LOGIC ;
   din    : IN STD_LOGIC_VECTOR( width - 1 DOWNTO 0);
   dout   : OUT STD_LOGIC_VECTOR( width - 1 DOWNTO 0)
);
END ENTITY;

ARCHITECTURE RTL OF Nxiaod IS

COMPONENT xiaod IS
PORT
(
   clk    : IN STD_LOGIC ;
   reset   : IN STD_LOGIC ;
   din    : IN STD_LOGIC ;
   dout   : OUT STD_LOGIC
);
END COMPONENT;

BEGIN

g1: FOR i IN 0 to width - 1 GENERATE
ux: xiaod port map( clk => clk, reset => reset, din => din(i), dout => dout(i));

END GENERATE;

END RTL;

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