原创 一年前写的键盘扫描代码。给大家看看吧，想要的拿去

fpga的矩阵键盘还是不错的东西，速度也挺快的，个人写了四五个版本，就贴上一个版本吧。

里面不允许同时按下两个，使用的是16*16的格式，呵呵，要改的自己去改啊

代码如下。风格完全是我自己的风格

///下面是key module 主要是扫描用的

module key(clk,col,key_num,row);
parameter wide = 16;
parameter val_wide = 16;

input clk;
input [wide-1:0] col;
output [val_wide-1:0] key_num;
output [wide-1:0] row;
parameter s0 = 0,
     s1 = 5'h1,
     s2 = 5'h2,
     s3 = 5'h3,
     s4 = 5'h4,
     s5 = 5'h5,
     s6 = 5'h6,
     s7 = 5'h7,
     s8 = 5'h8,
     s9 = 5'h9,
     s10 = 5'ha,
     s11 = 5'hb,
     s12 = 5'hc,
     s13 = 5'hd,
     s14 = 5'he,
     s15 = 5'hf,
     s16 = 5'h10;
    
    
parameter en_counter = 32'h7a120;
parameter scan     = 4'h0,
    read_temp = 4'h1,
    read     = 4'h2,
    delay     = 4'h4,
    delay1    = 4'h8;

reg [wide-1:0]     row;

reg [3:0]      state ;
reg [3:0]      row_value ;

reg [4:0]       S_col;
reg [3:0]      statement;
reg [3:0]      next_state;

reg [31:0]       counter;
reg [31:0]       counter1;

reg rst = 1;

always @(posedge clk)
   rst <= 0;
  
always @ ( posedge clk )
if ( rst )
   counter <= 0 ;
else if ( statement == delay )
    begin
     if ( counter == en_counter )
      counter <= 0 ;
     else
      counter <= counter + 1'b1 ;
    end  

always @ ( posedge clk )
if ( rst )
   counter1 <= 0 ;
else if ( statement == delay1 )
    begin
     if ( counter1 == en_counter )
      counter1 <= 0 ;
     else
      counter1 <= counter1 + 1'b1 ;
    end    
  

always @ ( posedge clk )
if ( rst )
   statement <= scan ;
else
   statement <= next_state;

always @ ( rst or statement or counter or counter1 or col )
if (rst)
   next_state = scan ;
else
   case ( statement )
   scan :     next_state = read_temp ;
  
read_temp : if ( col )
       next_state = delay ;
      else
       next_state = scan   ;
      
   read : if ( col )
       next_state = read   ;
      else
       next_state = delay1 ;
      
   delay : if ( counter == en_counter )
       next_state = read ;
      else
       next_state = delay;
      
   delay1: if ( counter1 == en_counter )
       next_state = scan ;
      else
       next_state = delay1 ;
      
   default:    next_state = scan ;
   endcase
  
always @ (posedge clk)
if(rst)
   begin
    row_value <=0;
    S_col <= 1;
    state <= 0;
    row <= 16'h8000;
   end
else
case(statement)
scan:    begin
       row   <= {row[0],row[15:1]};
       state <= state + 1;
       row_value <=16'h0;
       S_col <= 1;
      end
read_temp : ;
  
read:   if (col)
      begin
       case(col)
       16'h8000: begin row_value <=state;S_col <= s1; end
       16'h4000: begin row_value <=state;S_col <= s2; end
       16'h2000: begin row_value <=state;S_col <= s3; end
       16'h1000: begin row_value <=state;S_col <= s4; end
       16'h0800: begin row_value <=state;S_col <= s5; end
       16'h0400: begin row_value <=state;S_col <= s6; end
       16'h0200: begin row_value <=state;S_col <= s7; end
       16'h0100: begin row_value <=state;S_col <= s8; end
       16'h0080: begin row_value <=state;S_col <= s9; end
       16'h0040: begin row_value <=state;S_col <= s10; end
       16'h0020: begin row_value <=state;S_col <= s11; end
       16'h0010: begin row_value <=state;S_col <= s12; end
       16'h0008: begin row_value <=state;S_col <= s13; end
       16'h0004: begin row_value <=state;S_col <= s14; end
       16'h0002: begin row_value <=state;S_col <= s15; end
       16'h0001: begin row_value <=state;S_col <= s16; end
       default : begin row_value <=16'h0;S_col <= 1 ; end
       endcase
      end
      else
                  begin row_value <=16'h0;S_col <= 1 ; end
     
delay :   ;
     
delay1:     ;

default:   ;

endcase     

Value_out instance_name (
    .row_value(row_value),
    .S_col(S_col),
    .clk(clk),
    .rst(rst),
    .key_value(key_num)
    );
endmodule

下面是value—out 模块

module Value_out(row_value, S_col, clk, rst, key_value);
    input [3:0] row_value;
    input [4:0] S_col;
    input clk;
    input rst;
    output [15:0] key_value;
reg [15:0] key_value;

always @(posedge clk)
if(rst)
   key_value <= 0;
else
   key_value <= (row_value<<4) + S_col-1 ;

上面的都是经过实际工程项目的调试的，放心用吧

给个问题吧，为什么我要使用一个read_temp 的状态呢？

呵呵，这个里面发现能有很大的空间值得研究