原创 spartan3e starter kit prom 出现问题，搞了一个上午

spartan3e的开发板 今天出现了一点问题，然后去网上一搜，发现全都是一些提问和旁观者，没有一个合理的解释，然后我自己去找，通过对文件UG230的分析，知道impact的集中编程时序，以及板子对于跳线的使用，确保了M[2：0] 全是000的时候，发现问题不是出在编程器的上面，中文论坛和网站上基本没有合理的解释，于是我蹭到了Xilinx的官方论坛，人家老美的问题还真是详细啊，所有的输出内容都给了出来，如下所示：

I tried to program the PROM and here is the log-data:

// *** BATCH CMD : Program -p 1 -e -v -loadfpga -u aaaaaaaa -defaultVersion 0
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Erasing device...
PROGRESS_START - Starting Operation.
'1': Erasure completed successfully.
'1': Programming device...
done.
'1': Putting device in ISP mode...done.
'1': Putting device in ISP mode...done.
'1': Verifying device...done.
'1': Verification completed successfully.
'1': Calculated checksum matches expected checksum, 003a8bd84
'1': Putting device in ISP mode...done.
'1': Setting usercode...done.
'1': Putting device in ISP mode...done.
'1': Putting device in ISP mode...done.
'1': Setting user-programmable bits...
done.
'1': Putting device in ISP mode...done.
'1': Starting FPGA Load with Prom Data...INFO:iMPACT:563 - '1':Please ensure proper connections as specified by the data book ...
'1': Programming completed successfully.
'1': Programming completed successfully.
PROGRESS_END - End Operation.
Elapsed time =     14 sec.

What does the red info mean? Could this be my problem or is it just for info? I didnt′t get a warning or error message.

// *** BATCH CMD : ReadStatusRegister -p 2
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Reading status register contents...
CRC error                                         :         0
Decryptor security set                            :         0
DCM locked                                        :         1
DCI matched                                       :         1
legacy input error                                :         0
status of GTS_CFG_B                               :         0
status of GWE                                     :         0
status of GHIGH                                   :         0
value of MODE pin M0                              :         1
value of MODE pin M1                              :         1
value of MODE pin M2                              :         1
value of CFG_RDY (INIT_B)                         :         1
DONEIN input from DONE pin                        :         0
IDCODE not validated while trying to write FDRI   :         0
write FDRI issued before or after decrypt operation:         0
Decryptor keys not used in proper sequence        :         0

I hope you can get some useful information from the register.

I tried to pulse PROG the FPGA - it worked fine but this is programming the FPGA isn′t it. Programming the FPGA directly always worked.

I put some User Code (aaaaaaaa) into the PROM. The usercode can be verified from the PROM but not from FPGA (ffffffff).

I will have a look at the debug guide, thank you. 

Thanks in advance for your help!

通过查询文件 ug332查询master-slaver的工作模式学到很多，

也得到一些很重要的提示，后面查询了文档ug230的原理图部分，

特别是在UG230的文档上在chapter16上的cpld得到了答案，说明我的错误时CPLD的文件重写出现问题了，因此从官网上下了这个文件下来，其实自己写也很简单，纯组合电路就可以实现控制了。

下面是生成好的jed文件，下下来解压然后直接用impact把它编译就可以了