原创 FPGA 边沿检测模块

最近在弄了个模块，先贴上

module JCY(clk,din,rst_n,falling,raising,double);
input clk;
input rst_n;
input din;
output falling;//下降沿
output raising;//上升沿
output double;//双沿
reg falling,raising,double;
reg temp;

always @ (posedge clk or negedge rst_n)
if(!rst_n)
 begin
 falling<=1'b0;
 raising<=1'b0;
 double<=1'b0;
 temp<=1'b0;
 end
else
 begin
 temp<=din;
 raising<=din & (~temp);
 falling<=(~din) & temp;
 double<=din^temp;
 end
endmodule

如上图所示，这样检测到的结果会延时，因此下面是上面的更正

module JCY(clk,din,rst_n,falling,raising,double);
input clk;
input rst_n;
input din;
output falling;
output raising;
output double;
reg falling,raising,double;
reg temp;

always @ (posedge clk or negedge rst_n)
 if(!rst_n)
  temp<=1'b0;
 else
  temp<=din;

always@(falling or temp or double or raising)
 begin
  raising<=din & (~temp);
  falling<=(~din) & temp;
  double<=din^temp;
 end
endmodule