原创 UART！--原创

经过自己的努力

    UART 测试完毕！

    `timescale 1ns/1ns

module UART_RX(clk,rst,RXD,data_out,TXD_busy,ERROR);

input clk;

input rst;

input RXD;

output[7:0] data_out;

   reg[7:0] data_out;

   reg[9:0] data_out_buff;

output TXD_busy;

   reg TXD_busy;

output ERROR;

   reg ERROR;

parameter[3:0]IDLE=4'b0000,

    S0=4'b0001,

S1=4'b0010,

S2=4'b0011,

S3=4'b0100,

S4=4'b0101,

S5=4'b0110,

S6=4'b0111,

S7=4'b1000,

    S8=4'b1001,

S9=4'b1010,

  STOP=4'b1011;

// output[3:0] state;

   reg[3:0] state;

   reg[2:0] bit_collect;

// output[7:0] CNT;

   reg[7:0] CNT;

reg RXD_buff;

reg RXD_falling;

always@(posedge clk or negedge rst)

begin

if(!rst)

RXD_falling<=0;

else

begin

RXD_buff<=RXD;

RXD_falling<=(~RXD)&RXD_buff;

end

end

always@(posedge clk or negedge rst)

begin

if(!rst)

state=IDLE;

else

begin

case(state)

IDLE:

begin

if(RXD_falling)

begin

TXD_busy=1'b1;

state=S0;

CNT=1'b1;

end

else

begin

TXD_busy=1'b0;

state=IDLE;

CNT=1'b1;

end

end

S0:

begin

CNT=CNT+1'b1;

if(CNT=='d6)

bit_collect[0]=RXD;

if(CNT=='d7)

bit_collect[1]=RXD;

if(CNT=='d8)

bit_collect[2]=RXD;

if( (bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]) )

data_out_buff[0]=RXD;

if(CNT=='d15)

begin

if(data_out_buff[0]==0)

begin

state=S1;

ERROR=1'b0;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S1:

begin

CNT=CNT+1'b1;

if(CNT=='d22)

bit_collect[0]=RXD;

if(CNT=='d23)

bit_collect[1]=RXD;

if(CNT=='d24)

bit_collect[2]=RXD;

if(CNT=='d31)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[1]=RXD;

ERROR=1'b0;

state=S2;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S2:

begin

CNT=CNT+1'b1;

if(CNT=='d38)

bit_collect[0]=RXD;

if(CNT=='d39)

bit_collect[1]=RXD;

if(CNT=='d40)

bit_collect[2]=RXD;

if(CNT=='d47)

begin

if( (bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[2]=RXD;

ERROR=1'b0;

state=S3;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S3:

begin

CNT=CNT+1'b1;

if(CNT=='d54)

bit_collect[0]=RXD;

if(CNT=='d55)

bit_collect[1]=RXD;

if(CNT=='d56)

bit_collect[2]=RXD;

if(CNT=='d63)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[3]=RXD;

ERROR=1'b0;

state=S4;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S4:

begin

CNT=CNT+1'b1;

if(CNT=='d70)

bit_collect[0]=RXD;

if(CNT=='d71)

bit_collect[1]=RXD;

if(CNT=='d72)

bit_collect[2]=RXD;

if(CNT=='d79)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[4]=RXD;

ERROR=1'b0;

state=S5;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S5:

begin

CNT=CNT+1'b1;

if(CNT=='d86)

bit_collect[0]=RXD;

if(CNT=='d87)

bit_collect[1]=RXD;

if(CNT=='d88)

bit_collect[2]=RXD;

if(CNT=='d95)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[5]=RXD;

ERROR=1'b0;

state=S6;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S6:

begin

CNT=CNT+1'b1;

if(CNT=='d102)

bit_collect[0]=RXD;

if(CNT=='d103)

bit_collect[1]=RXD;

if(CNT=='d104)

bit_collect[2]=RXD;

if(CNT=='d111)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[6]=RXD;

ERROR=1'b0;

state=S7;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S7:

begin

CNT=CNT+1'b1;

if(CNT=='d118)

bit_collect[0]=RXD;

if(CNT=='d119)

bit_collect[1]=RXD;

if(CNT=='d120)

bit_collect[2]=RXD;

if(CNT=='d127)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[7]=RXD;

ERROR=1'b0;

state=S8;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S8:

begin

CNT=CNT+1'b1;

if(CNT=='d134)

bit_collect[0]=RXD;

if(CNT=='d135)

bit_collect[1]=RXD;

if(CNT=='d136)

bit_collect[2]=RXD;

if(CNT=='d143)

begin

if((bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

begin

data_out_buff[8]=RXD;

ERROR=1'b0;

state=S9;

end

else

begin

state=STOP;

ERROR=1'b1;

end

end

end

S9:

begin

CNT=CNT+1'b1;

if(CNT=='d140)

bit_collect[0]=RXD;

if(CNT=='d141)

bit_collect[1]=RXD;

if(CNT=='d142)

bit_collect[2]=RXD;

if( (bit_collect[0]==bit_collect[1])

&&(bit_collect[1]==bit_collect[2])

&&(bit_collect[1]==bit_collect[0]))

data_out_buff[9]=RXD;

if(CNT=='d159)

begin

if(data_out_buff[9]==1)

begin

data_out=data_out_buff[8:1];

ERROR=1'b0;

state=IDLE;

CNT='d0;

TXD_busy<=1'b0;

end

else

begin

data_out=8'b0;

TXD_busy=1'b0;

state=IDLE;

ERROR=1'b1;

end

end

end

STOP:

begin

if(CNT=='d159)

begin

state<=IDLE;

ERROR=1'b1;

CNT='d0;

end

else

CNT=CNT+1'b1;

end

endcase

end

end

endmodule

`timescale 1ns/1ns module UART_TX(clk,rst,data_in,EN,TXD,TXD_busy);

input clk; input rst;

input[7:0] data_in;

input EN;

output TXD;

 reg TXD; r

eg[7:0] data_buff;

output TXD_busy;

reg TXD_busy;

parameter[3:0]IDLE=4'b0000,

START=4'b0001,

S0=4'b0011,

S1=4'b0111,

S2=4'b0110,

 S3=4'b0100,

S4=4'b1100,

S5=4'b1010,

S6=4'b1110,

STOP=4'b1111;

// output[3:0] state; reg[3:0] state;

 always@(posedge clk or negedge rst)

 if(!rst) state<=IDLE;

 else

begin

case(state)

IDLE:

begin

if(EN)

begin

data_buff<=data_in;

TXD<=1'b0;

TXD_busy<=1'b1;

state<=START;

end

 else

begin

TXD<=1'b1;

TXD_busy<=1'b0;

 state<=IDLE;

end

end

START:

begin

TXD<=data_buff[0];

state<=S0;

end

S0:

begin

TXD<=data_buff[1];

state<=S1;

end S1:

begin TXD<=data_buff[2];

state<=S2;

end

S2:

begin

 TXD<=data_buff[3];

state<=S3;

end

S3:

begin

TXD<=data_buff[4];

 state<=S4;

end

 S4:

 begin

TXD<=data_buff[5];

state<=S5;

end

S5:

 begin TXD<=data_buff[6]; state<=S6; end

S6: begin TXD<=data_buff[7]; state<=STOP; end

STOP: begin TXD<=1'b1; TXD_busy<=1'b0; state<=IDLE; end

endcase end endmodule