Can't find design entity "fir91"问题
在打开工程时找不到fir91.v源文件
版本号：Quartus v13.0
寻找很久 终于发现是因为前边注释太多 导致，删除前边很长的注释即可。
程序如下。
// megafunction wizard: %FIR Compiler v9.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// fir91_ast
// ============================================================
// Generated by FIR Compiler 9.1 [Altera, IP Toolbench 1.3.0 Build 222]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2009 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module fir91 (
clk,
reset_n,
ast_sink_data,
coef_set,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
coef_set_in,
coef_we,
coef_in,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error);
input clk;
input reset_n;
input [15:0] ast_sink_data;
input coef_set;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
input coef_set_in;
input coef_we;
input [18:0] coef_in;
output [37:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
fir91_ast fir91_ast_inst(
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(ast_sink_data),
.coef_set(coef_set),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.coef_set_in(coef_set_in),
.coef_we(coef_we),
.coef_in(coef_in),
.ast_source_data(ast_source_data),
.ast_sink_ready(ast_sink_ready),
.ast_source_valid(ast_source_valid),
.ast_source_error(ast_source_error));
endmodule
// =========================================================
// FIR Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
//
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// =========================================================
// RELATED_FILES: fir91_st.v, fir91_constraints.tcl, fir91_ast.vhd, fir91.v, fir91_ast.vhd, fir91.v;
// IPFS_FILES: fir91.vo;
// =========================================================
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