原创 fir91.v滤波器 Can't find design entity

 2013-11-18 11:17  5248 16 16 分类: FPGA/CPLD

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	Can't find design entity "fir91"问题</div>
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	在打开工程时找不到fir91.v源文件</div>
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	版本号：Quartus  v13.0</div>
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	寻找很久 终于发现是因为前边注释太多  导致，删除前边很长的注释即可。</div>
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	程序如下。</div>
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	// megafunction wizard: %FIR Compiler v9.1%</div>
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	// GENERATION: XML</div>
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	// ============================================================</div>
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	// Megafunction Name(s):</div>
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	// <span class="Apple-tab-span" style="white-space:pre;"> </span>fir91_ast</div>
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	// ============================================================</div>
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	// Generated by FIR Compiler 9.1 [Altera, IP Toolbench 1.3.0 Build 222]</div>
<div>
	// ************************************************************</div>
<div>
	// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!</div>
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	// ************************************************************</div>
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	// Copyright (C) 1991-2009 Altera Corporation</div>
<div>
	// Any megafunction design, and related net list (encrypted or decrypted),</div>
<div>
	// support information, device programming or simulation file, and any other</div>
<div>
	// associated documentation or information provided by Altera or a partner</div>
<div>
	// under Altera's Megafunction Partnership Program may be used only to</div>
<div>
	// program PLD devices (but not masked PLD devices) from Altera.  Any other</div>
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	// use of such megafunction design, net list, support information, device</div>
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	// programming or simulation file, or any other related documentation or</div>
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	// information is prohibited for any other purpose, including, but not</div>
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	// limited to modification, reverse engineering, de-compiling, or use with</div>
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	// any other silicon devices, unless such use  explicitly licensed under</div>
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	// a separate agreement with Altera or a megafunction partner.  Title to</div>
<div>
	// the intellectual property, including patents, copyrights, trademarks,</div>
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	// trade secrets, or maskworks, embodied in any such megafunction design,</div>
<div>
	// net list, support information, device programming or simulation file, or</div>
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	// any other related documentation or information provided by Altera or a</div>
<div>
	// megafunction partner, remains with Altera, the megafunction partner, or</div>
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	// their respective licensors.  No other licenses, including any licenses</div>
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	// needed under any third party's intellectual property, are provided herein.</div>
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	module fir91 (</div>
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	clk,</div>
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	reset_n,</div>
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	ast_sink_data,</div>
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	coef_set,</div>
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	ast_sink_valid,</div>
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	ast_source_ready,</div>
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	ast_sink_error,</div>
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	coef_set_in,</div>
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	coef_we,</div>
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	coef_in,</div>
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	ast_source_data,</div>
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	ast_sink_ready,</div>
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	ast_source_valid,</div>
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	ast_source_error);</div>
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	 </div>
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	 </div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>clk;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>reset_n;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>[15:0]<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_sink_data;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>coef_set;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_sink_valid;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_source_ready;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>[1:0]<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_sink_error;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>coef_set_in;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>coef_we;</div>
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	input<span class="Apple-tab-span" style="white-space:pre;"> </span>[18:0]<span class="Apple-tab-span" style="white-space:pre;"> </span>coef_in;</div>
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	output<span class="Apple-tab-span" style="white-space:pre;"> </span>[37:0]<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_source_data;</div>
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	output<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_sink_ready;</div>
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	output<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_source_valid;</div>
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	output<span class="Apple-tab-span" style="white-space:pre;"> </span>[1:0]<span class="Apple-tab-span" style="white-space:pre;"> </span>ast_source_error;</div>
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	 </div>
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	 </div>
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	fir91_ast<span class="Apple-tab-span" style="white-space:pre;"> </span>fir91_ast_inst(</div>
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	.clk(clk),</div>
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	.reset_n(reset_n),</div>
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	.ast_sink_data(ast_sink_data),</div>
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	.coef_set(coef_set),</div>
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	.ast_sink_valid(ast_sink_valid),</div>
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	.ast_source_ready(ast_source_ready),</div>
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	.ast_sink_error(ast_sink_error),</div>
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	.coef_set_in(coef_set_in),</div>
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	.coef_we(coef_we),</div>
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	.coef_in(coef_in),</div>
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	.ast_source_data(ast_source_data),</div>
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	.ast_sink_ready(ast_sink_ready),</div>
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	.ast_source_valid(ast_source_valid),</div>
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	.ast_source_error(ast_source_error));</div>
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	endmodule</div>
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	 </div>
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	// =========================================================</div>
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	// FIR Compiler Wizard Data</div>
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	// ===============================</div>
<div>
	// DO NOT EDIT FOLLOWING DATA</div>
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	// @Altera, IP Toolbench@</div>
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	// Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.</div>
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	// </div>
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	// =========================================================</div>
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	// RELATED_FILES: fir91_st.v, fir91_constraints.tcl, fir91_ast.vhd, fir91.v, fir91_ast.vhd, fir91.v;</div>
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	// IPFS_FILES: fir91.vo;</div>
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	// =========================================================</div>
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	 </div>

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