原创 乒乓机制

        以前用RAM静态采集了AD的数据，当时时间太紧那种结构只适合用来验证AD采集的正确性，不能用于动态显示和控制。前一段时间写了一个乒乓机制的程序，用来控制两个FIFO分别进行读写，跟适合我们的测试系统，不过还有一些小问题还需要解决，边调试边解决吧！

主要的控制部分的程序给出，欢迎拍砖！

-------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------  Entity Declaration------------------
ENTITY control IS
 PORT
 (
  clk : IN STD_LOGIC;
  a_full : IN STD_LOGIC;
  a_empty : IN STD_LOGIC;
  b_empty : IN STD_LOGIC;
  b_full : IN STD_LOGIC;
  a_q : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  a_wr : OUT STD_LOGIC;
  b_wr : OUT STD_LOGIC;
  a_rd : OUT STD_LOGIC;
  b_rd : OUT STD_LOGIC;
  b_q : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  a_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
  b_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
  q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
 );
 
END control;

--  Architecture Body

ARCHITECTURE control_architecture OF control IS
 TYPE states IS (S0,S1,S2,S3);
   SIGNAL current_state,next_state : states;
BEGIN
TRS:PROCESS(clk)
    BEGIN
      IF (CLK='1' AND CLK'EVENT)THEN current_state<=next_state;
      END IF;
END PROCESS TRS;
REG:PROCESS(a_empty,b_empty,a_full,b_full)
    BEGIN
      CASE current_state IS
        WHEN S0 => IF(a_empty='1' AND a_full='0'AND b_empty='1')THEN next_state <=S1;
                     ELSE next_state <=S0;
                   END IF;
        WHEN S1 => IF(a_full='1' AND b_empty='1' AND b_full='0')THEN next_state <=S2;
                     ELSE next_state <=S1;
                   END IF;
        WHEN S2 => IF(a_empty='1' AND b_full='1')THEN next_state <=S3;
                     ELSE next_state <=S2;
                   END IF;
        WHEN S3 => IF(a_full='1' AND b_empty='1')THEN next_state <=S2;
                     ELSE next_state <=S3;
                   END IF;   
      END CASE;
    END PROCESS REG;
COM:PROCESS(current_state)  
    BEGIN
      CASE current_state IS
      WHEN S0 => a_wr<='0';a_rd<='0';b_wr<='0';b_rd<='0';
      WHEN S1 => a_wr<='1';a_rd<='0';b_wr<='0';b_rd<='0';a_data<=data;
      WHEN S2 => a_wr<='0';a_rd<='1';b_wr<='1';b_rd<='0';q<=a_q;b_data<=data;
      WHEN S3 => a_wr<='1';a_rd<='0';b_wr<='0';b_rd<='1';q<=b_q;a_data<=data;
      END CASE;
END PROCESS COM;             
END control_architecture;