原创 50M频率计数器(另一个版本)

与前一版本相比，在硬件上，两者各有千秋，在软件上，这个版本提供的代码是C语言的。

从作者提供的原理图上看，主控CPU为AT90S2313，信号采集部分采用两片74HC590(8位计数器)级联。输入信号未经任何处理，直接接入74HC590。
关于软件部分，我大概考虑了一下，没有深究，也没有拜读作者的源代码，
可能与实际情况不符。采样数值的读取由定时器发起，在计算真实采样频率时，根据不同的定时器间隔，采用不同的“倍乘”系数，达到扩展测量范围的目的。举例
来说，如果定时器间隔为10mS，则真正的频率为采样值*100；如果定时器间隔为100mS，则真正的频率为采样值*10。
实现自动换档，有很多技巧，需要根据实际情况灵活对待。只要措施得当，这两个版本都可实现自动换档。

This is another project which fullfills a need. I once built a frequency counter using plain TTL chips. That was long before the
CMOS HC versions, even before LS was available.

It could measure up to 50 MHz and worked quite okay, but the TTL chips was extremely power hungry. I think there was about
20-25 TTL chips on that monster.

Well, but the old counter is now somewhere in the shed, and as I now again needed a counter, I did a bit more modern design.

It uses only 4 chips - 3 HC TTL's and an Atmel At90S2313 microcontroller. It has a 5 digit LED display plus one used as a band
indicator. Even with the LED display, the current consumption is less than 50 mA.

It counts up to at least 52 MHz. I couldn't find any signal source in the lab that could supply more than 52 MHz, so it may
go a bit higher, but the fClock(typ) for the HC590 is about 35-40 MHz, so you shouldn't really count (no pun intended) on more.

I got the idea from an article I saw on the net. I think it was a Circuit Cellar article. I had a look at the code, and it
sounded like a quick and simple counter solution. I don't know what chips it used, as I never saw the schematic, but here's
my implementation :

The hi-tech frequency counter board

Sneaking up behind.

The schematic is quite straightforward. There are two major parts, the display multiplexing and the counter stage.

A 8-bit "databus" is constructed from the lower 4 bits of PORTD and the upper 4 bits of PORTB on the 2313. This peculiar
arrangement is necessary, as we need the OC1 output on PB3 for gating the counter stage.

The displays are 3-digit 7-segment common-cathode displays. They are multiplexed by supplying the segment data from
the databus, and selecting the current digit with a 'HC138 dataselector, which is controlled by 3 I/O lines from
the 2313.


The two 'HC590 counters are counting the input pulses and supplies the
count to the 2313
on the databus. Each counter can be read separately using the OE_L and
OE_H lines. The counters are cleared using the CLR signal.
The counters are gated using the OC1 (Output Compare 1) signal from the
2313. By varying the duration of the gate time, the counter can be made
autoranging, and handle a large frequency span.

Click image to see a larger schematic.

The software for the counter is written in C-code, as speed is not an issue. All high-speed handling is done by the external
counters and the Timer1 in the 2313.

The method of measuing a frequency is simple. First, the counters are enabled for 1 mS. If the count is larger than
4096 (4.096 MHz), the count is shown on the display, and a new count is made. If less that 4096, we can get better
resolution with a larger gate time, so we try 10 mS. Again, if the count is larger than 4096 (409.6 KHz), the count
is shown, otherwise we try 100mS, or down to 1 S.

The range for each gate time is :

The display multiplexing is handled by an interrupt routine running on Timer0 every 2 mS. Three global variables are
used to control the displayed value, the decimal point and range indicator. The range indicator uses the segments A,
G and D (top, middle and bottom) in the last display to indicate Hz, kHz and MHz.

View schematics

Download C-code

 
 


Comments are always welcome at jesperh@telia.com


 
 

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