原创 TILE64™ PROCESSOR FAMILY

 2007-8-26 14:54  3354 2 2 分类: MCU/ 嵌入式

TILE64™ PROCESSOR FAMILY

The TILE64™ family of multicore processors delivers immense compute performance to drive the latest generation of embedded applications. This revolutionary processor features 64 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network. Each tile is a complete full-featured processor, including integrated L1 & L2 cache and a non-blocking switch that connects the tile into the mesh. This means that each tile can independently run a full operating system, or multiple tiles taken together can run a multi-processing operating system like SMP Linux.

TILE64 Processor The TILE64™ processor family slashes board real estate and system cost by integrating a complete set of memory and I/O controllers, thus eliminating the need for an external North Bridge or South Bridge. It delivers scalable performance, power efficiency and low processing latency in an extremely compact footprint.

With a standard ANSI C programming environment, developers can leverage their existing software investment as well as utilize the vast body of Open Source code available. Tiles can be grouped into clusters to apply the appropriate amount of horsepower to each application. Since multiple operating system instances can be run on the TILE64™ simultaneously, it can replace multiple CPU subsystems for both the data plane and control plane.

Applications

Advanced Networking: The TILE64 processor provides the Ethernet line interfaces as well as the entire data plane processing for intelligent network services such as:

Unified Threat Management (UTM)
Network Security Appliances
In-line L4-7 deep packet inspection
Network Monitoring

Digital Video: The TILE64 processor also excels at digital video processing, easily taking the place of multiple DSPs as well as the networking components for:

Video Conferencing
Video-on-Demand (VoD) Servers
Video surveillance
Media 'Head-End' services

	Feature	Enables
Massively Scalable Performance	• 8 X 8 grid of identical, general purpose processor cores (tiles) • 3-way VLIW pipeline for instruction level parallelism • 5 Mbytes of on-chip Cache • 192 billion operations per second (32-bit) • 27 Tbps of on-chip mesh interconnect • Up to 50 Gbps of I/O bandwidth	• 10 Gbps Snort® processing • 20+ Gbps iptables (firewall) • 20+ Gbps nProbe • 16 X 16 SAD at 540 MBlocks/s • H.264 HD video encode for two streams of 720p @ 30 Fps
Power Efficiency	• 600MHz – 900MHz operating frequency • 170 – 300mW per core • Idle Tiles can be put into low-power sleep mode • Power efficient inter tile communications	• Highest performance per watt • Simple thermal management & power supply design • Small System form factor • Low BOM cost
Integrated Solution	• Four DDR2 memory controllers with optional ECC • Two 10GbE XAUI MAC/PHY interfaces • Two 4-lane 10Gbps PCI-e MAC/PHY interfaces • Two GbE MAC interfaces • Flexible I/O interface	• Reduces BOM cost – standard interfaces included on-chip • Dramatically reduced board real estate • Direct interface to leading L2-L3 switch vendors
Ease of Programming	• ANSI standard C compiler • Supports SMP Linux with 2.6 kernel • iLib API's for efficient inter-tile communication • Advanced profiling and debugging designed for multicore programming	• Run off-the-shelf C programs • Leverage investment in existing code • Reduce debug and optimization time • Faster time to production code • Standard multicore communication mechanisms