原创 Tensilica's ESL Design

ESL Design

Designing systems at a higher level of abstraction than RTL (Verilog or VHDL) is becoming the modern approach for system design, and can both save effort and reduce risk. However, there are many methods for designing at higher levels (often called “electronic system level” or ESL design). These include high-level synthesis, SOC architecture assembly and simulation (for both single and multi-processor based designs), and functional algorithm design. How can you be sure the methods you pick will get you the high-quality results you need?

Try Tensilica’s ESL methods. Tensilica will help you quickly select or produce a single or mulit-processor architecture with the performance your application needs. You don’t have to understand how to design a microprocessor. Instead, all you need to understand is your application – what you want the system to do.

With Tensilica’s configurable and extensible processors, there are several ways to achieve the time-saving advantages of ESL design. The first is a high-level synthesis approach:

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2. You can run your C/C++ program through our XPRES Compiler, which will automatically configure an Xtensa processor for you.
   
3. You can write your own TIE (Tensilica Instruction Extension) instructions to extend the processor.
   
4. You can combine both of the above techniques by using the output of the XPRES Compiler as a starting point and then adding further refinements to the XPRES-generated TIE code using your special knowledge of the application problem—knowledge not contained in the C or C++ program.

Tensilica guarantees the resulting hardware will be correct, saving you valuable verification time and allowing your design engineers to spend more time on design exploration and less time on verification.

More complex applications may require a multi-processor SOC architecture. Here the application is partitioned by the designer into multiple tasks which may be mapped onto several target processors. Although application partitioning is manual, once the system architect has an initial notion, a number of different system modeling approaches may be used:

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2. You can build a system level model with our XTMP modelling environment. This provides models of memories, connectors, and queues that can be interconnected with configured processors into an overall system model that runs either as a SystemC model or as a C/C++ model. The processor and device interfaces are at the transaction level.
   
3. Alternatively, you can interface the transaction-level modelling of our ISS/XTMP environment to several different SystemC-based SOC architecture assembly and simulation tools. This allows other IP blocks to be more easily integrated.
   
4. If you have legacy RTL blocks as part of your system, our Mentor Seamless model generation allows the use of this HW-SW co-verification tool for building models.

Once a system model is built, you can explore different task partitionings and different numbers of processor configurations. These may include fixed configurations from our Diamond series of processors as well as processors you have configured yourself. Different task partitionings, numbers and configurations of processors and mappings of tasks to processors may be explored. You may use XPRES-generated instruction extensions or your own for any processor you configure into the system model.

The big advantage to using Tensilica processor(s) for ESL design is that the result is a single or group of 32-bit RISC processor(s). They are programmable and can run any C or C++ program. Functional changes can be made in firmware after the chip is produced. This means that complex state machines are implemented in firmware running on the processor(s) – greatly reducing verification time.

If you solve a design problem using traditional, manual RTL design to produce hardwired hardware, you can’t make software changes after the chip is made. You’re faced with an expensive redesign if conditions or standards change. And conditions and standards always change.

A number of ideas on ESL design using Tensilica cores are discussed in the book “Designing SOCs with Configured Cores: Unleashing the tensilica Xtensa and Diamond Cores” by Steve Leibson. Chapter five in particular discusses tools for complex SOC designs.

See the article, "ESL Requirements for Configurable Processor-based Embedded System Design" by Grant Martin.