原创 reset

Designing power-up reset sequence and reset structures in a chip is a critical task and there are many issues one needs to be aware of. Incorrect reset generation can cause intermittent failures that are hard to debug and in some cases can also make a chip DOA (Dead on Arrival).

<?XML:NAMESPACE PREFIX = O />

In this post, we will look at asynchronous/synchronous resets, reset synchronizers and also factors that may affect reset sequence in a chip. Most of the information presented here is derived from Cliff Cummings et. al. excellent paper and the reader is strongly recommended to read the paper at his leisure.

Resets can be either synchronous or asynchronous and each flip-flop has a timing window during which the reset cannot change transition. Recovery time is known as the minimum time the reset should be stable BEFORE the active clock edge (setup time); (The reset recovery time is a type of setup timing condition on a flip-flop that defines the minimum amount of time between the de-assertion of reset and the next rising clock edge)

 while Removal is the minimum time the reset should be stable AFTER the active clock edge (hold time).

Advantages of using Synchronous resets are :

• 
  
• The reset is active only on active clock edge.
  
• Fewer number of gates (although negligible)
  
• Timing analysis is easier as the reset is synchronous to the clock.

A major disadvantage of synchronous reset design is that the clock should be running at the time of reset. In some chips, this may not be feasible due to gated clocks or due to requirements of the design.

Advantages of using Asynchronous resets are :

• 
  
• No extra logic on the datapath making timing closure easier
  
• No clock required at the time of reset

The problem with asynchronous resets is that they can cause flops to go metastable, hence care must be taken at the time of assertion or deassertion of reset. Another issue is that timing analysis should include checks for recovery and removal times.

Reset Synchronizer

A novel technique to overcome the issues with asynchronous resets is to use Reset synchronizers. A reset synchronizer ensures that the reset removal does not cause any metastable problems – it resets the design asynchronously ( i.e. without a running clock) while the deassertion is synchronous!

Reset synchronizer

A reset synchronizer circuit is shown above, the two flops are dual stage synchronizers to synchronize the reset to the clock. On assertion of the chip reset, the synchronizer output drives the internal reset to the flops in the design. Deassertion can only happen during the next active edge. An important point to note is that the second flop in the synchronizer cannot go metastable as both the input and output points are both low when the reset is removed.

The two flops in the reset synchronizer should not be made scannable for DFT and a bypass mux is added at the output of the reset synchronizer to control the reset in test modes. Also note that a separate reset synchronizer will be required for each clock domain.

Another important requirement in many multi-clock domains is sequencing of resets – i.e. reset in one clock domain must be deasserted prior to reset in another clock domain. The author has come across designs where this requirement was neglected or overlooked causing critical issues in Silicon. A circuit below using reset synchronizers illustrates this.