原创 Altera推荐的双层叠复位方式

2009-3-18 18:36 6312 7 7 分类: FPGA/CPLD

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       异步复位会影响寄存器的recovery时间,引起设计的稳定性问题。尤其对于状态机的无意识的复位导致进入不确定的状态。


 


       下面介绍一种更为可靠的异步复位、同步释放的双缓冲电路。该电路由两个同一时钟沿触发的层叠寄存器组成,该时钟必须和目标寄存器是一个时钟域。


 


//---------------------------------------


//两级层叠复位产生,低电平复位


reg rst_nr1,rst_nr2;


 


always @ (posedge clk or negedge rst_n)


       if(!rst_n) rst_nr1 <= 1'b0;


       else rst_nr1 <= 1'b1;


 


always @ (posedge clk or negedge rst_n)


       if(!rst_n) rst_nr2 <= 1’b0;


       else rst_nr2 <= rst_nr1;


      


//---------------------------------------   


//异步复位,同步释放


always @ (posedge clk or negedge rst_nr2)


       if(!rst_nr2) b <= 1'b0;


       else b <= a1;


      


always @ (posedge clk or negedge rst_nr2)


       if(!rst_nr2) c <= 1'b0;


       else c <= a2;


 


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点击看大图 


//---------------------------------------


//两级层叠复位产生,高电平复位


reg rst_r1,rst_r2;


 


always @ (posedge clk or posedge rst)


       if(rst) rst_r1 <= 1'b1;


       else rst_r1 <= 1'b0;


 


always @ (posedge clk or posedge rst)


       if(rst) rst_r2 <= 1’b0;


       else rst_r2 <= rst_r1;


      


//---------------------------------------   


//异步复位,同步释放


always @ (posedge clk or posedge rst_r2)


       if(rst_r2) b <= 1'b0;


       else b <= a1;


      


always @ (posedge clk or posedge rst_r2)


       if(rst_r2) c <= 1'b0;


       else c <= a2;


 



点击看大图 


 

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