原创 分频器的verilog HDL描述

偶数倍分频：偶数倍分频应该是大家都比较熟悉的分频，通过计数器计数是完全可以实现的。如进行N倍偶数分频，那么可以通过由待分频的时钟触发计数器计数，当计数器从0计数到N/2-1时，输出时钟进行翻转，并给计数器一个复位信号，使得下一个时钟从零开始计数。以此循环下去。这种方法可以实现任意的偶数分频。
module odd_division(clk,rst,count,clk_odd);
  input        clk,rst;
  output       clk_odd;
  output[3:0]  count;
  reg          clk_odd;
  reg[3:0]     count;
  parameter    N = 6;
  
    always @ (posedge clk)
      if(! rst)
        begin
          count <= 1'b0;
          clk_odd <= 1'b0;
        end
      else      
        if ( count < N/2-1)
          begin        
            count <= count + 1'b1;          
          end
        else
          begin      
            count <= 1'b0;
            clk_odd <= ~clk_odd;    
          end
endmodule

   奇数倍分频：归类为一般的方法为：对于实现占空比为50%的N倍奇数分频，首先进行上升沿触发进行模N计数，计数从零开始，到（N－1）/2进行输出时钟翻转，然后经过（N-1）/2再次进行翻转得到一个占空比非50%奇数n分频时钟。再者同时进行下降沿触发的模N计数，到和上升沿过（N-1）/2时，输出时钟再次翻转生成占空比非50%的奇数n分频时钟。两个占空比非50%的n分频时钟相或运算，得到占空比为50%的奇数n分频时钟。
module even_division(clk,rst,count1,count2,clk_even);
  input        clk,rst;
  output[3:0]  count1,count2;
  output       clk_even;
  reg[3:0]     count1,count2;
  reg          clkA,clkB;
  wire         clk_even;
  parameter    N = 5;

    assign clk_re   = ~clk;
    assign clk_even = clkA | clkB;
  
    always @(posedge clk)
      if(! rst)
        begin
          count1 <= 1'b0;
          clkA  <= 1'b0;          
        end
      else
        if(count1 < (N - 1))
          begin
            count1 <= count1 + 1'b1;            
            if(count1 == (N - 1)/2)
              begin
                clkA <= ~clkA;
              end              
          end        
        else
          begin
            clkA <= ~clkA;
            count1 <= 1'b0;
          end          
        
  always @ (posedge clk_re)
    if(! rst)
      begin
        count2 <= 1'b0;
        clkB  <= 1'b0;
      end
    else
      if(count2 < (N - 1))
        begin
          count2 <= count2 + 1'b1;            
            if(count2 == (N - 1)/2)
              begin
                clkB <= ~clkB;
              end              
        end        
      else
        begin
          clkB <= ~clkB;
          count2 <= 1'b0;
        end          
endmodule