tag 标签: megacore

相关资源
  • 所需E币: 5
    时间: 2019-12-25 17:30
    大小: 1.27MB
    上传者: 二不过三
    SerialliteMegaCoreFunctionUserGuide……
  • 所需E币: 5
    时间: 2019-12-25 17:04
    大小: 322.94KB
    上传者: rdg1993
    ViterbiCompilerMegaCoreFunctionUserGuide……
  • 所需E币: 4
    时间: 2020-1-6 12:43
    大小: 62.96KB
    上传者: rdg1993
    UpdatingSimulationModelsforthePOS-PHYLevel4MegaCoreFunction……
  • 所需E币: 3
    时间: 2019-12-24 19:31
    大小: 1.2MB
    上传者: 238112554_qq
    【应用手册】AN541:SerialLiteIIHardwareDebuggingGuideTheSerialLiteIIMegaCore®functionisalightweight,chip-to-chipprotocolsuitableforbothpacketandstreamingdatainchip-to-chip,board-to-board,andbackplaneapplications.Itofferslowprotocoloverhead,lowgatecount,andminimaldatatransferlatency.Itprovidesreliable,high-speedtransfersofpacketsbetweendevicesoverseriallinks.TheSerialLiteIIprotocoldefinespacketencapsulationatthelinklayer,anddataencodingatthephysicallayer.Theprotocalintegratestransparentlywithexistingnetworks,withoutsoftwaresupport.TheSerialLiteIIMegaCorefunctionprovidesasimpleandlightweightwaytomovedatafromonepointtoanotherreliablyathighspeeds.Itcomprisesaseriallinkofupto16bondedlaneswithlogictoprovideanumberofbasicandoptionallinksupportfunctions.TheAtlanticinterfaceistheprimaryaccessfordeliveringandreceivingdata.AN541:SerialLiteIIHardwareDebuggingGuideAugust2008AN-541-1.0IntroductionTheSerialLiteIIMegaCorefunctionisalightweight,chip-to-chipprotocolsuitableforbothpacketandstreamingdatainchip-to-chip,board-to-board,andbackplaneapplications.Itofferslowprotocoloverhead,lowgatecount,andminimaldatatransferlatency.Itprovidesreliable,high-speedtransfersofpacketsbetweendevicesoverserial……
  • 所需E币: 3
    时间: 2019-12-24 19:11
    大小: 434.94KB
    上传者: 238112554_qq
    【应用笔记】PCIExpress宏功能函数的外部PHY支持(ExternalPHYSupportinPCIExpressMegaCoreFunctions)PCIExpress编译器产生用户自定义的PCIExpressMegaCore函数,使得你能够使用它来设计PCIExpress终点。ThePCIExpressCompilergeneratescustomizedPCIExpressMegaCore®functionsthatyoucanusetodesignPCIExpressendpoints.ThePCIExpressMegaCorefunctionsarecompliantwithPCIExpressBaseSpecificationRevision1.1orPCIExpressBaseSpecificationRevision1.0a.Thefunctionsimplementallrequiredandmostoptionalfeaturesofthespecificationforthetransaction,datalink,andphysicallayers.ExternalPHYSupportinPCIExpressMegaCoreFunctionsMay2007,ver.1.0ApplicationNote443IntroductionThePCIExpressCompilergeneratescustomizedPCIExpressMegaCorefunctionsthatyoucanusetodesignPCIExpressendpoints.ThePCIExpressMegaCorefunctionsarecompliantwithPCIExpressBaseSpecificationRevision1.1orPCIExpressBaseSpecificationRevision1.0a.Thefunctionsimplementallrequiredandmostoptionalfeaturesofthespe……
  • 所需E币: 3
    时间: 2019-12-24 19:09
    大小: 291.26KB
    上传者: 238112554_qq
    【应用笔记】DDR和DDR2SDRAM纠错码参考设计(DDRandDDR2SDRAMECCReferenceDesign)本应用笔记描述了一种使用AlteraDDR和DDR2SDRAM控制器MegaCore功能函数实现的纠错码(error-correctingcode,ECC)模块。Thisapplicationnotedescribesanerror-correctingcode(ECC)blockforusewiththeAlteraDDRandDDR2SDRAMcontrollerMegaCorefunctions.AlteraalsosuppliesanECCreferencedesign,whichusestheECCblockwiththeDDR2SDRAMcontrollerMegaCorefunctionandaMicronMT9HTF3272AY-53EB3DIMMat200MHz.ThereferencedesignrunsonaStratix®IIHigh-SpeedDevelopmentBoard.DDRandDDR2SDRAMECCReferenceDesignVersion1.0,June2006ApplicationNote415IntroductionThisapplicationnotedescribesanerror-correctingcode(ECC)blockforusewiththeAlteraDDRandDDR2SDRAMcontrollerMegaCorefunctions.AlteraalsosuppliesanECCreferencedesign,whichusestheECCblockwiththeDDR2SDRAMcontrollerMegaCorefunctionandaMicronMT9HTF3272AY-53EB3DIMMat200MHz.ThereferencedesignrunsonaStratixIIHigh-SpeedDevelopmentBoard.……
  • 所需E币: 5
    时间: 2019-12-24 18:53
    大小: 2.93MB
    上传者: 978461154_qq
    【应用笔记】AN328:StratixII、StratixIIGX、andArriaGX器件和DDR2SDRAM的接口(AN328:InterfacingDDR2SDRAMwithStratixII,StratixIIGX,andArriaGXDevices)本应用笔记提供关于DDR2和Stratix®II、StratixIIGX和Arria®GX接口的信息ThisapplicationnoteprovidesinformationaboutinterfacingDDR2SDRAMwithStratix®II,StratixIIGX,andArria®GXdevices.ItincludesdetailsaboutsupportedmodesandguidelinesfordesigningwiththesedevicesanddescribesAltera’srecommendeddesignflowforimplementingaDDR2SDRAMmemoryinterfaceonaStratixII,StratixIIGX,orArriaGXFPGA.AN328:InterfacingDDR2SDRAMwithStratixII,StratixIIGX,andArriaGXDevicesOctober2009AN-328-6.0IntroductionThisapplicationnoteprovidesinformationaboutinterfacingDDR2SDRAMwithStratixII,StratixIIGX,andArriaGXdevices.ItincludesdetailsaboutsupportedmodesandguidelinesfordesigningwiththesedevicesanddescribesAltera’srecommendeddesignflowforimplementinga……
  • 所需E币: 3
    时间: 2019-12-24 11:11
    大小: 97.5KB
    上传者: givh79_163.com
    基于AlteraMegaCore实现FFT的方法基于AlteraMegaCore实现FFT的方法0引言FFT(快速傅里叶变换)是计算离散傅里叶变换(DFT)的高效算法,它把计算N点DFT的乘法运算量从N2次下降到N/2log2N次。FFT的出现对数字信号处理的发展起着至关重要的作用,它可应用于傅里叶变换所能涉及的任何领域,为广泛应用数学方法处理数字信号开辟了新局面[1]。传统的FFT实现方法是通过软件(软件编程)和硬件(专用芯片ASIC)这两种方法来实现,而近年来,FPGA发展十分迅速,这给FFT设计提供了一个新思路[2]。为了更好地满足设计人员的需要,各大公司相继推出了IP模块,本文提出了一种采用Altera公司的IPCoreFFTMegaCore来实现FFT的简单方法。1FFTMegaCore核的性能Altera公司的FFTMegaCore是一个高性能、高参数化的快速傅里叶变换处理器,可以高效的完成FFT和IFFT运算,支持的器件系列包括StratixⅡ、StratixGX、StratixⅡGX、Stratix、Cyclone、CycloneⅡ以及CycloneⅢ等,采用基2/4频域抽取(DIF)FFT算法,运算长度从64到16384,使用嵌入式内存,系统最大时钟频率大于300MHz。FFT处理器可以设置两种不同的引擎结构:四输出和单输出,结构图如图1和图2所示[3]。为了增加FFT兆核函数的总吞吐量,也可以在一个FFT兆核函数变量中使用多个并行引擎。复取样数据X[k,m]从内部存储器并行读出并由变换开关(SW)重新排序,排序后的取样数据由基4处理器处理并得到复数输出G[k,m],由于基4按频率抽选(DIF)分解方法固有的数字特点,在蝶形处理器[4]输出上仅需……