【应用笔记】DDR和DDR2 SDRAM纠错码参考设计(DDR and DDR2 SDRAM ECC Reference Design) 本应用笔记描述了一种使用AlteraDDR和DDR2 SDRAM控制器MegaCore功能函数实现的纠错码(error-correcting code,ECC)模块。 This application note describes an error-correcting code (ECC) block for use with the Altera DDR and DDR2 SDRAM controller MegaCore functions. Altera also supplies an ECC reference design, which uses the ECC block with the DDR2 SDRAM controller MegaCore function and a Micron MT9HTF3272AY-53EB3 DIMM at 200 MHz. The reference design runs on a Stratix® II High-Speed Development Board. DDR and DDR2 SDRAM ECC Reference Design Version 1.0, June 2006 Application Note 415 Introduction This application note describes an error-correcting code (ECC) block for use with the Altera DDR and DDR2 SDRAM controller MegaCore functions. Altera also supplies an ECC reference design, which uses the ECC block with the DDR2 SDRAM controller MegaCore function and a Micron MT9HTF3272AY-53EB3 DIMM at 200 MHz. The reference design runs on a Stratix II High-Speed Development Board. ……