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【应用笔记】在APEX器件中使用ClockLock和ClockBoostPLL功能(UsingtheClockLock&ClockBoostPLLFeaturesinAPEXDevices)APEX20k器件具有ClockLock和ClockBoost功能,该功能使用PLL来提高性能并提供时钟频率综合。APEXTM20KdeviceshavetheClockLockTMandClockBoostTMfeatures,whichusephase-lockedloops(PLLs)toincreaseperformanceandprovideclock-frequencysynthesis.TheClockLockfeatureminimizesclockdelayandclockskewwithinthedevice,reducingclock-to-outputandsetuptimeswhilemaintainingzeroholdtimes.TheClockBoostfeatureallowsdesignerstoruntheinternallogicofthedeviceatafasterorslowerratethantheinputclockfrequency.Thistechniquesimplifiesboarddesignbecausetheclocktreeontheboarddoesnothavetodistributeahigh-speedsignal.Throughtheuseoftime-domainmultiplexing,theClockBoostfeatureallowsthedesignertoimprovedeviceareaefficiencybysharingresourceswithinthedevice.UsingtheClockLock&ClockBoostPLLFeaturesinAPEXDevicesNovember2003,ver.2.6ApplicationNote115IntroductionAPEXTM20KdeviceshavetheClockLockTMandClockBoostTMfeatures,whichusephase-lockedloops(PLLs)toincreaseperformanceandprovideclock-frequencysynthesis.TheClockLockfeatureminimizesclockdelayandclockskewwithinthedevice,reducingclock-to-outputandsetupti……