【应用笔记】在APEX器件中使用ClockLock和ClockBoost PLL功能(Using the ClockLock & ClockBoost PLL Features in APEX Devices) APEX 20k器件具有ClockLock和ClockBoost功能，该功能使用PLL来提高性能并提供时钟频率综合。 APEXTM 20K devices have the ClockLockTM and ClockBoostTM features, which use phase-locked loops (PLLs) to increase performance and provide clock-frequency synthesis. The ClockLock feature minimizes clock delay and clock skew within the device, reducing clock-to-output and setup times while maintaining zero hold times. The ClockBoost feature allows designers to run the internal logic of the device at a faster or slower rate than the input clock frequency. This technique simplifies board design because the clock tree on the board does not have to distribute a high-speed signal. Through the use of time-domain multiplexing, the ClockBoost feature allows the designer to improve device area efficiency by sharing resources within the device. Using the ClockLock & ClockBoost PLL Features in APEX Devices November 2003, ver. 2.6 Application Note 115 Introduction APEXTM 20K devices have the ClockLockTM and ClockBoostTM features, which use phase-locked loops (PLLs) to increase performance and provide clock-frequency synthesis. The ClockLock feature minimizes clock delay and clock skew within the device, reducing clock-to-output and setup ti……