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016617641894IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.41,NO.8,AUGUST2006AVersatile90-nmCMOSCharge-PumpPLLforSerDesTransmitterClockingAlvinL.S.Loke,SeniorMember,IEEE,RobertK.Barnes,SeniorMember,IEEE,TinTinWee,SeniorMember,IEEE,MichaelM.Oshima,SeniorMember,IEEE,CharlesE.Moore,Member,IEEE,RonaldR.Kennedy,Member,IEEE,andMichaelJ.Gilsdorf,SeniorMember,IEEEAbstract―Thispaperpresentsalow-jittercharge-pumpphase-lockedloop(PLL)builtinstandard90-nmCMOSfor1to10Gb/swirelineSerDestransmitterclocking.ThePLLemploysaprogrammabledual-pathlooplterwithintegralpathandresistorlesssample-resetproportionalpaththatareindependentlycontrolledforexiblesettingofclosed-loopbandwidthandpeaking.Frequencyissynthesiz……