016617641894 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking Alvin L. S. Loke, Senior Member, IEEE, Robert K. Barnes, Senior Member, IEEE, Tin Tin Wee, Senior Member, IEEE, Michael M. Oshima, Senior Member, IEEE, Charles E. Moore, Member, IEEE, Ronald R. Kennedy, Member, IEEE, and Michael J. Gilsdorf, Senior Member, IEEE Abstract―This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop lter with integral path and resistorless sample-reset proportional path that are independently controlled for exible setting of closed-loop bandwidth and peaking. Frequency is synthesiz……