标签: fpag，数字ic，笔试题

8 、用 HDL 设计一个模块。完成有符号数除法，被除数为 16-bit 整数，除数为 8-bit 整数，输出 8-bit 商和 8-bit 余数，所有输入输出都是有符号数。 module div_16(clk,rst_n,a,b,c,d,div_out,p,div_c); input clk; input rst_n; input a; input b; output c; output d; output div_out; output p; output div_c;   wire div_a; wire div_b; wire p; reg div_c; reg div_d; wire div_out;   assign div_a = (a == 0) ? a : {a ,~a +1'b1}; assign div_b = (b == 0) ? b : {b ,~b +1'b1}; assign p = a ^ b ;   always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin div_c = 8'b0; div_d = 8'b0; // div_d = 8'b0; end else begin div_c = div_a / {div_b }; div_d = div_a % div_b ; end end //assign div_c = div_a / div_b ; //assign div_d = div_a % div_b ; assign div_out = {p,div_c }; assign c = (div_out == 0) ? div_out : {div_out ,~div_out +1'b1}; assign d = div_d; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin div_c = 8'b0; div_d = 8'b0; // div_d = 8'b0; end else begin div_c = div_a / {div_b }; div_d = div_a % div_b ; end end //assign div_c = div_a / div_b ; //assign div_d = div_a % div_b ; assign div_out = {p,div_c }; assign c = (div_out == 0) ? div_out : {div_out ,~div_out +1'b1}; assign d = div_d;   endmodule     这样写的话基本就对了，还有一种写法是针对使用 verilog-2001 的，使用 signed 有符号定义，但 modelsim 仿真有点问题，我先贴出代码和仿真图先： module div_8(clk,rst_n,a,b,c,d); input clk; input rst_n; input signed a; input signed b; output signed c; output signed d;   assign c = a / b; assign d = a % b;   endmodule     你们估计看到了，若是使用这种写法的话，得到的模都是负值，后来我查了资料，模值是和第一个数的正负一样，就是和被除数是一样的。除非都是正值，不然还是有问题的。