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2015-3-21 13:36
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定义:不用关心时序的路径。 用户可以利用各种方法将伪路径 排除在时序分析之外 。 quartus II handbook False Paths S pecifying a false path in your design removes the path from timing analysis. Use the set_false_path command to specify false paths in your design. You can specify either a pointto-point or clock-to-clock path as a false path. For example, a path you should specify as false path is a static configuration register that is written once during power-up initialization, but does not change state again. Although signals from static configuration registers often cross clock domains, you may not want to make false path exceptions to a clock-to-clock path, because some data may transfer across clock domains. However, you can selectively make false path exceptions from the static configuration register to all endpoints. set_false_path - from - to 用户可以在assignment Editor中设置独立的伪路径 减除约束(Cut Timing) (1)cut off feedback from i/o pins 缺省时选中改选项,这样在Timequest Analyser中,就不会分析 所示,从双向IO口返回来的路径,即C路径,而会正常分析路径A,B。如果去掉该选项,则会分析路径C。 (2)Cut Clear and Preset Paths 默认情况选中该选项。这样时序分析时候,不会分析如图灰色箭头的路径: 它们都是到达寄存器的 异步清零端 、 置位端 。 如果设计中是同步清零/置位信号,那么工具会分析这些路径的时序。 (3) Cut off Read During Write Signal Paths 默认选中该选项。时序分析时候,不会分析从 写使能寄存器 穿过 ESB (Embedded system block)到达 目的寄存器 的路径。 如果不选,则会分析该路径。 (4)Cut Paths between Unrelated Clocks 默认选中,减除非相关时钟间路径的时序分析。 在图中,inst1~inst4路径不会在时序报告中体现。