W; 1 8 0 3 01 7 7 75 9 ABB LXN1604-6 3BHL000986P7000、UNS4881b,V4 3BHE009949R0004、UNS3670A-Z V2 HIEE205011R0002、UNS2980c-ZV4、UNS2882A 3BHE003855R0001、UNS2881b-P,V1 3BHE009319R0001、UNS2880b-P,V2 3BHE014967R0002、UNS2880B-P V1、UNS0887A-P 3BHE008128R0001、UNS0881a-P,V1 3BHB006338R0001ABB LXN1604-6 3BHL000986P7000、UNS4881b,V4 3BHE009949R0004LXN1604-6 3BHL000986P7000邮箱-VMEbus接口提供四个可从两个服务器访问的32位邮箱微处理器和提供处理器间接口的VMEbus表达邮箱具有中断的能力当VMEbus访问微处理器时。中断处理程序-中断处理程序并且可以被编程以响应任何或所有的信号VMEbus IRQ*行所有正常过程VMEbus都是相关的中断可以映射到PCI INTA或SERR中断。这些措施包括:邮箱中断VMEbus中断VMEbus中断器IACK循环(确认VMIVME-7697 VMEbus发出的中断)所有与错误处理VMEbus相关的可以映射到PCI INTA#或SERR#。注:PCI SERR启动SBC NMI。这些措施包括:ACFAIL*中断BERR*中断SYSFAIL*中断中断处理程序具有相应的状态/ID为每个IRQ*中断注册。一旦处理器接收到消息在IRQ*中,它请求VMEbus, 一旦获得授权,它将执行以下操作:该级别的IACK循环。一旦IACK循环结束完成,状态/ID存储在相应的在ID寄存器中设置适当的中断状态位并且生成PCI中断。这个PCI中断可以映射到PCI INTA#或SERR1)对输入/输出点的选择 ABB LXN1604-6 3BHL000986P7000、UNS4881b,V4 3BHE009949R0004、UNS3670A-Z V2 HIEE205011R0002、UNS2980c-ZV4、UNS2882A 3BHE003855R0001、UNS2881b-P,V1 3BHE009319R0001、UNS2880b-P,V2 3BHE014967R0002、UNS2880B-P V1、UNS0887A-P 3BHE008128R0001、UNS0881a-P,V1 3BHB006338R0001ABB LXN1604-6 3BHL000986P7000、UNS4881b, V4 3bhe09949r0004lxn1604-6 3bhl000986p7000 mailbox VMEbus interface provides four 32-bit mailbox microprocessors that can be accessed from two servers and the VMEbus expression mailbox that provides inter processor interface has the ability to interrupt when the VMEbus accesses the microprocessor. Interrupt handler - interrupt handler and can be programmed to respond to any or all signals VMEbus IRQ * all normal process VMEbus are related interrupts can be mapped to PCI inta or SERR interrupts. These measures include: mailbox interrupt VMEbus interrupt VMEbus interrupter iack cycle (confirm the interrupt sent by vmivme-7697 VMEbus) all the VMEbus related to error handling can be mapped to PCI inta # or SERR #. Note: PCI SERR starts SBC NMI. These measures include: acfail * interrupt Berr * interrupt sysfail * interrupt interrupt handler has corresponding status / ID to register each IRQ * interrupt. Once the processor receives the message in IRQ *, it requests VMEbus, and once authorized, it will perform the following operations: iack loop at this level. Once the iack cycle is completed, the status / ID is stored in the corresponding interrupt status bit set in the ID register and the PCI interrupt is generated. This PCI interrupt can be mapped to the selection of input / output points by PCI inta # or serr1)