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时间: 2019-12-24 19:08
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【应用笔记】理解StratixII器件的PLL时序(UnderstandingPLLTimingforStratixIIDevices)StratixII器件有多达12个的PLL,可以为片上时钟管理、外部系统时钟管理以及高速I/O接口,提供强健的时钟管理和综合。Stratix®IIdeviceshaveupto12phase-lockedloops(PLLs)thatproviderobustclockmanagementandsynthesisforon-chipclockmanagement,externalsystemclockmanagement,andhigh-speedI/Ointerfaces.TheStratixIIPLLishighlyversatileandcanbeusedasazerodelaybuffer,jitterattenuator,lowskewfan-outbuffer,andasafrequencysynthesizer.TotakeadvantageofthenumerousfeaturesandcapabilitiesprovidedbytheStratixIIPLLs,afullunderstandingofallreportsandanalysisperformedbytheQuartus®IITimingAnalyzerisnecessary.Thisapplicationnoteprovidesdetails,examples,andguidelinesonhowtoreadandunderstandthevariousTimingAnalysisreportsrelatingtoPLLs,andhowtheanalysisisperformedbytheTimingAnalyzer.ThisapplicationnoteisapplicabletodesignsthattargetStratixIIdevicesusingtheQuartusIIsoftwareversion5.1andearlier.UnderstandingPLLTimingforStratixIIDevicesMarch2006,ver.1.0ApplicationNote411IntroductionStratixIIdeviceshaveupto12phase-lockedloops(PLLs)thatproviderobustclockmanagementandsynthesisforon-chipclockmanagement,externalsystemclockmanagement,andhigh-speedI/Ointerfaces.TheStratixIIPLLishighlyversatileandcanbeusedasazerodelaybuffer,jitterattenuator,lowskewfan-outbuffer,andasafrequencysynthesizer.Totakeadvantageofthenumerous……