标签: time-interleaving

Abstract:Interleavingmultipleanalog-to-digitalconverters(ADCs)isusuallyperformedwiththeintenttoincreaseaconverterseffectivesamplerate,especiallyiftherearenooronlyfewoff-the-shelfADCsavailablethatfulfillthedesiredsample,linearityandACrequirementsofsuchapplications.However,time-interleavingdataconvertersisnotaneasytask,becauseevenwithperfectlylinearcomponents,gain/offsetmismatchesandtimingerrorscancauseundesiredspursintheoutputspectrum.Thefollowingarticleprovidesvaluableinsightintothetheoreticalapproachoftime-interleavedanalog-to-digitalconvertersandthekindofroadblocks(andhowtocompensateforthem)adesignerusuallyencounterswhenbuildingatime-interleavedsystem.Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200……

摘要：交错多个模拟-数字转换器（ADC）通常采用增加一个转换器，有效样本率的意图，尤其是如果有没有或只有很少可用的现成的ADC完成所需的样品，线性交流等应用的要求。然而，时间交错的数据转换器是不是一件容易的事，因为即使有完美的线性元件，增益/偏移不匹配和时序错误可能会导致在输出频谱中意外马刺。时间交错的模拟-数字转换器和路障（以及如何补偿他们）的理论方法，设计师通常会建立一个时间交错系统时遇到下面的文章提供了宝贵的见解。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200……

摘要：交错多个模拟-数字转换器（ADC）通常采用增加一个转换器，有效样本率的意图，尤其是如果有没有或只有很少可用的现成的ADC完成所需的样品，线性交流等应用的要求。然而，时间交错的数据转换器是不是一件容易的事，因为即使有完美的线性元件，增益/偏移不匹配和时序错误可能会导致在输出频谱中意外马刺。时间交错的模拟-数字转换器和路障（以及如何补偿他们）的理论方法，设计师通常会建立一个时间交错系统时遇到下面的文章提供了宝贵的见解。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200……