标签: vhdl

书籍介绍 相关的预览图片都放在百度云盘, pan.baidu.com/s/1pJZkUBx, 以下只是缩略图. 声明 自己翻译的一些电子工程,计算机方面的外文书籍, 想挣点奶粉钱. 购买方式        书籍价格已经在标题中, 只有方式有点复杂. 首先登陆百度网盘pan.baidu.com/s/1pJZkUBx, 在"洋文馆-阅读器"路径下, 找到专用阅读器freeme(只支持xp,win7), 将阅读器安装到你的电脑上, 然后打开freeme阅读器, 点击"关于注册"菜单,在弹出对话框中,找到HOSTID, 一共32个字符, 有两种方法可联系博主. 1. 推荐方法, 发Email到doc_sale@163.com, 将HOSTID告知博主, 博主将会提供一个淘宝链接给你, 或是直接转账给 博主的支付宝账号(doc_sale@163.com), 并将转账流水号一并寄出, 之后博主可将书籍发送到你的邮箱.     2. 给博主写站内信, 但是博主无法保证能够及时回复你.

VGA(视频图形阵列Video Graphics Array)是IBM在1987年随PS/2机一起推出的一种视频传输标准，具有分辨率高、显示速率快、颜色丰富等优点，在彩色显示器领域得到了广泛的应用。 目前 VGA技术的应用还主要基于 VGA显示卡的，而在一些既要求显示彩色高分辨率图像又不使用计算机的设备上，VGA技术的应用却很少。本文对基于 FPGA/CPLD的嵌入式 VGA显示的实现方法进行了研究。 基于 FPGA/CPLD的嵌入式 VGA显示系统，可以在不使用 VGA显示卡的情况下实现 VGA图像的显示和控制。该系统具有成本低、结构简单、应用灵活的优点。 1 基于 FPGA/CPLD的嵌入式 VGA显示系统简介 通用 VGA显示卡系统主要由控制电路、显示缓存区和视频 BIOS程序三个部分组成。其控制电路主要完成时序发生、显示缓冲区数据操作等功能;显示缓冲区提供显示数据缓存空间;视频BIOS作为控制程序固化在显示卡的 ROM中。在基于FPGA/CPLD的嵌入式VGA显示系统的设计中，可以使用很少的资源，就产生 VGA各种控制信号，达到显示彩色高分辨率图像的要求，而不需用 VGA显示卡和计算机设备。图 1是基于 FPGA/CPLD的嵌入式 VGA显示系统的结构框图，图中FPGA采用的是Altera公司Cyclone II系列的EP2C35F672C这款 FPGA.Cyclone II器件采用 90nm、低 K值电介质工艺，通过使硅片面积最小化，可以在单芯片上支持复杂的数字系统。EP2C35F672C该芯片提供了 33216个逻辑单元 ,包括了嵌入式 18*18位乘法器、专用外部存储器接口电路、 4KB嵌入式存储器件、4个锁相环和高速差分 I/O等功能。该芯片的工作频率和引脚 IO等资源都能很好的满足本系统的要求。FPGA的工作时钟为 54MHz。 VGA接口芯片采用了 ADV7125，该芯片是美国 ADI公司生产的高速视频数模转换芯片，其像素扫描时钟频率有 50MHz、140 MHz、270 MHz、330MHz四个等级。ADV7125在单芯片上整合了三组 8位高速 D/A转换器，可以分别处理红、绿、蓝视频数据，特别适用于高分辨率模拟接口的显示终端和要求高速 D/A转换的应用系统。 ADV7125的输入及控制信号非常简单：3组 8位的数字视频数据输入端，分别对应 RGB视频数据，数据输入端采用标准 TTL电平接口;4条视频控制信号线包括复合同步信号 SYNC、消隐信号 BLANK、白电平参考信号 REF WHITE和像素时钟信号 CLOCK;外接一个 1.23 V数模转换参考电压源和 1个输出满度调节。只有 4条输出信号线：模拟 RGB信号采用高阻电流源输出方式，可以直接驱动 75Ω同轴传输线。 图1 基于FPGA/CPLD的嵌入式VGA显示系统框图 2 模块划分与模块功能定义 FPGA中包含了四个工作模块： VGA时序发生器模块、VGA图像显示调色板模块、数据存储器和数据读写控制器。由于 ADV7125内部没有颜色的转换器 ,所以当数据存储器中的数据为 YUV信号时，就要把 YUV信号转换成 RGB信号,这一功能就是由 VGA图像显示调色板模块完成的，当显示数据为 RGB信号时，数据可以直接传输到 ADV7125，不需调色板进行颜色转换。数据存储器和数据读写控制器解决了显示数据的来源和数据的存储。用 FPGA对图像进行存储和整理，并产生驱动电路需要的各种控制波形由视频控制器对颜色缓冲器进行扫描，其中视频控制器可以读取像素颜色，用这些颜色来控制输出设备的亮度。 VGA时序发生器模块产生显示器所需的时序，这是完成设计的关键，时序稍有偏差，显示必然不正常，甚至会损坏彩色显示器。 【分页导航】 第1页： 基于FPGA/CPLD的VGA显示系统简介 第2页： VGA时序分析 第3页： VGA显示器在雷达图像显示中的应用 3 VGA时序分析 显示器采用光栅扫描方式，即轰击荧光屏的电子束在 CRT(阴极射线管)屏幕上从左到右(受水平同步信号 HSYNC控制)、从上到下(受垂直同步信号 VSYNC控制)做有规律的移动。光栅扫描又分逐行扫描和隔行扫描。隔行扫描指电子束在扫描时每隔一行扫一线，完成一屏后再返回来扫描剩下的线，与电视机的原理一样。隔行扫描的显示器扫描闪烁的比较厉害，会让使用者的眼睛疲劳。目前微机所用显示器几乎都是逐行扫描。逐行扫描是指扫描从屏幕左上角一点开始，从左向右逐点进行扫描，每扫描完一行，电子束回到屏幕的左边下一行的起始位置，在这期间，CRT对电子束进行消隐，每行结束时，用行同步信号进行行同步;当扫描完所有行，形成一帧时，用场同步信号进行场同步，并使扫描回到屏幕的左上方，同时进行行场消隐，开始下一帧的扫描。 完成一行扫描所需时间称为水平扫描时间，其倒数称为行频率;完成一帧(整屏)扫描所需的时间称为垂直扫描时间，其倒数为垂直扫描频率，又称刷新频率，即刷新一屏的频率。常见的有 60Hz、75Hz等。 图2 VGA的行时序 图3 VGA的场时序 VGA 显示器要正确显示图像关键还是如何实现 VGA时序。视频电子标准协会( VESA, Video Electronics Standards Association)对显示器时序进行了规范。 VGA的标准参考显示时序如图 2、图 3所示。行时序和场时序都需要产生同步脉冲(Sync a)、显示后沿 (Back porch b)、显示时序段(Display interval c)和显示前沿 (Front porch d)四个部分。 VGA工业标准显示模式要求：行同步、场同步都为负极性，即同步头脉冲要求是负脉冲。 VGA的行时序如图 2所示：每一行都有一个负极性行同步脉冲( Sync a)，是数据行的结束标志，同时也是下一行的开始标志。在同步脉冲之后为显示后沿 (Back porch b)，在显示时序段(Display interval c)显示器为亮的过程，RGB数据驱动一行上的每一个象素点，从而显示一行。在一行的最后为显示后沿(Back porch b)。在显示时序段( Display interval c)之外没有图像投射到屏幕时插入消隐信号。同步脉冲(Sync a)、显示后沿(Back porch b)和显示前沿(Front porch d)都是在行消隐间隔内( Horizontal Blanking Interval)，当行消隐有效时， RGB 信号无效，屏幕不显示数据。 VGA的场时序与 VGA的行时序基本一样，如图 3所示，每一帧的负极性帧同步脉冲(Sync a)是一帧的结束标志，同时也是下一帧的开始标志。而显示数据是一帧的所有行数据。 表 1：VGA行时序说明 表 2：VGA场时序说明 几种常用的时序参数如表 1和表2 所示，首先，根据显示器的性能选择一种合适的VGA模式，然后由象素时钟频率和图像分辨率计算出行总周期数，再把表 1和表 2中给出的 a、 b、c、d各时序段的时间按照象素计数脉冲源频率折算成时钟周期数。在 FPGA/CPLD中用计数器和触发器，以计算出的各时序段时钟周期数为基准，产生不同宽度和周期的脉冲信号，再利用它们的逻辑组合构成图 2和图 3中的 a、b、c、d各时序段以及 ADV7125的空白信号 BLANK和同步信号 SYNC。 一个示例就是 60Hz时 1280×1024分辨率显示的 VESA标准，在 60Hz时，屏幕每16.67毫秒更新一次。这个标准制定了帧大小，用它来定义分辨率和回扫次数之间的关系。对于分辨率大小为 1280×1024来说，帧的大小为 1688×1066，这个大小与像素时钟(Pixel Clock)有关，所谓像素时钟就是对像素的刷新频率。像素时钟为 1688×1066×60Hz 或者 108 兆 Hz(MHz)时，每个像素的刷新频率也就是大约 9.26纳秒，那么行频就为 60×1066=63960 行/秒，也就是用显示器的帧率乘以扫描线数量。可以用帧大小得到纵向回扫次数，为了得到纵向同步长度(Sync Length)，可以从纵向帧大小减去纵向分辨率，也就是 1066-1024=42。这样，纵向回扫花费的时间和在屏幕上绘出 42 条线的时间相同，对于纵向回扫来说需要的时间为 42×1688×9.26 纳秒(656 微秒)。 在显示时序段( Display interval c)，数据读写控制器从数据缓存区读取像素颜色，用这些颜色来控制输出设备(显示器)的亮度。一帧图像就准确的显示到 VGA显示器上。 【分页导航】 第1页： 基于FPGA/CPLD的VGA显示系统简介 第2页： VGA时序分析 第3页： VGA显示器在雷达图像显示中的应用 4、 VGA显示器在雷达图像显示中的应用 最初,雷达显示器到重要作用,在于使雷达接收机到数据以一种可视的形式表现出来。操作员可以轻易而精确地检测目标的出现,提取目标的位置信息。随着数字信号处理和数字数据处理的进步,越来越多的检测和信息提取过用电子方法自动完成,因此操作员的任务越来越少。现在雷达显示器更像电视监视器或计算机显示器,可以显示完整的连续场景。 雷达获取的信息是径向圆扫描方式属极坐标方式,所以早期船用雷达显示器是一种平面位置显示器,用极坐标表示,采用径向圆扫描方式,在这种扫描方式中,荧光屏上扫描线线径向扫描的数率取决于量程的大小。扫描线选转的速度取决于天线的转速。物标回波的亮度取决于回波视频的信号的幅度。物标回波及各种符号视频在屏上只能是天线每转一圈才能亮一下,在整个平面上亮度不均,且量程小,回波亮度越低,容易丢失小目标。精确保存物标距离信息非常勉强。目标分辨力差,在屏上画其他符号十分麻烦、困难,且符号量有限。 随着VGA显示器广泛应用,VGA显示器也开始应用在雷达显示上,但VGA显示起的扫描方式是从左到右到扫描和从上到下的帧扫,属于直角坐标的方式,而雷达获取的信息是径向圆扫描方式属极坐标方式,所以要实现雷达数据的 VGA显示首先要将雷达的极坐标信息转换成直角坐标信息存入存储器,再以直角扫描的方式从存储器中读出并显示出来。 VGA显示器可以将来自其他传感器得信息 ,例如其他雷达 :空中交通管制雷达应答系统 (ATCRBS) 、军用敌我识别 (IFF) 、低亮度 TV、前视红外 (FLIR),避免碰撞系统或来自民用或军用数据链的信息 ,都能组合到显示器上。除已处理雷达视频和原始视频外 ,雷达观测的区域地图及文字数字信息和图形也能添加到 VGA显示器上。 5、VGA显示器在雷达应用中的优点 与平面位置显示器相比,VGA显示器的在雷达图像显示上有了更大优势: 1)克服了平面位置显示器整个平面上亮度不均的缺点。实现了高亮度显示 2)避免显示器的图像的闪烁现象, 3)便于彩色显示 4)便于采用计算机显示终端技术 5)降低了成本,提高了可靠性 本文作者的创新点：在本设计中采用了 1280*1024的高分辨率显示 ,克服了早期低分辨率 VGA显示器雷达图像分裂和定位精度低的缺点。 【分页导航】 第1页： 基于FPGA/CPLD的VGA显示系统简介 第2页： VGA时序分析 第3页： VGA显示器在雷达图像显示中的应用

Generally speaking, there are only so many books I can read on RTL design before my eyes start to glaze over. Given that, there's the occasional gem that's well worth a read. One example is Sanjay Churiwala and Sapan Garg's Principles of VLSI RTL Design – A Practical Guide . There are several things to note about this book, starting with the fact that it's written by people who actually know what they are talking about (sadly, this is less common than one might hope). It's also important to understand that this book is not intended to teach you about any particular flavour of Register Transfer Level (RTL) hardware description language (HDL) like Verilog or VHDL. The idea is to teach you how to write better RTL. The thing is that there are a lot of very competent RTL designers when it comes to understanding an architectural or functional requirement and generating some RTL that will "do the job". What this book does is to take things to the next level by making you realise the downstream implications of any decisions you make while coding your RTL. For example, the way in which you code your RTL may affect testability, data synchronisation across clock domains, synthesisability, power consumption, routability, and so forth. Thus, the book walks us through various aspects associated with the following topics: * Ensuring RTL intent * Creating simulation-friendly RTL * Creating timing-analysis-friendly RTL * Creating clock-domain-crossing (CDC) RTL * Creating power-friendly RTL * Creating DFT-friendly RTL * Creating timing-exceptions friendly RTL * Creating congestion-conscious RTL This isn't a huge book – approximately 180 pages – but it's jam-packed with useful information. Also, it's written in a chatty, conversational style that will appeal to a lot of people (I personally like it a lot), but not to others (but they are grumpy little rascals and they don't count, so let's not worry about them). Both of the authors work for Atrenta, which provides SoC Realisation solutions for the semiconductor and electronic systems industries. I've always been impressed with the folks at Atrenta and with their solutions. With regard to this book, the various members of Atrenta's SpyGlass family of products are absolutely relevant with regard to ensuring "XYZ-friendly RTL" ... so one thing that really impressed me here is that the authors studiously managed to avoid mentioning Atrenta or SpyGlass in any way. It's so easy for a technical book to end up as a marketing exercise – so all credit to the authors for not falling into this trap. The list price is $129, although it's currently available for $102 from Amazon.com. On the one hand this is a tad expensive – on the other hand, if coding RTL is what you do a lot of and this makes you better at doing it, then $102 may be a bargain (especially if you can persuade your company to buy it for you). The bottom line is that if you spend a lot of time coding RTL, or if you are hoping to become a member of the RTL design engineering fraternity, then I think that reading this book would be well worth your time.  

Last January, I heard about an open source tool chain from Alex Kuznetsov in Moscow, Russia. He sent me an email saying:   Hi Max, I'm a developer of a new open-source software package dedicated to configurable IP cores packaging. The cores in question are basically RTL templates and therefore can be used both for FPGA and ASIC projects. The first public version was just released on Monday, January 24th. Maybe your readers would find this story interesting; in that case the official news release is as follows:   A new open-source software package, CoreTML framework, has been just released. It provides the necessary tools to create configurable RTL IP cores that produce VHDL/Verilog source based on user-supplied parameters.   CoreTML framework is arguably the first such piece of software that is both open-source and vendor-neutral. Currently configurable IP cores provide their own ways for the user to set up core parameters. Commercial EDA suites for FPGA design come with vendor-locked tools that can be used to generate only the IP cores developed by the EDA vendor or its partners. Being liberally licensed, CoreTML framework doesn't impose such a limitation and can be used for both commercial and noncommercial projects while achieving maximum portability.   A configurable IP core includes a definition of its parameters and a set of templates which are used to generate RTL source code. CoreTML templates are based on a specially designed Template Markup Language that allows the developer to supplement VHDL/Verilog source code with additional control tags which are recognized by the processing software. Template Markup Language leverages Lua programming language to provide a flexibility needed for the design of configurable IP cores.   CoreTML includes a Temlpate Markup Language processing tool, a graphical tool that can be used to configure the IP core, a couple of IP core examples and full documentation. CoreTML framework is licensed under the terms of the GNU Lesser General Public License (LGPL).   The development team also plans to develop a few more IP core examples to make a small configurable IP core library based on the CoreTML framework, as well as to make EDA integration smoother.   For more information please contact: Alex I. Kuznetsov Tel.: +7 916 8294445 (UTC+3) Email: ring0@ring0.co.cc Project website: http://coretml.sourceforge.net

Last January, I heard about an open source tool chain from Alex Kuznetsov in Moscow, Russia. He sent me an email saying:   Hi Max, I'm a developer of a new open-source software package dedicated to configurable IP cores packaging. The cores in question are basically RTL templates and therefore can be used both for FPGA and ASIC projects. The first public version was just released on Monday, January 24th. Maybe your readers would find this story interesting; in that case the official news release is as follows:   A new open-source software package, CoreTML framework, has been just released. It provides the necessary tools to create configurable RTL IP cores that produce VHDL/Verilog source based on user-supplied parameters.   CoreTML framework is arguably the first such piece of software that is both open-source and vendor-neutral. Currently configurable IP cores provide their own ways for the user to set up core parameters. Commercial EDA suites for FPGA design come with vendor-locked tools that can be used to generate only the IP cores developed by the EDA vendor or its partners. Being liberally licensed, CoreTML framework doesn't impose such a limitation and can be used for both commercial and noncommercial projects while achieving maximum portability.   A configurable IP core includes a definition of its parameters and a set of templates which are used to generate RTL source code. CoreTML templates are based on a specially designed Template Markup Language that allows the developer to supplement VHDL/Verilog source code with additional control tags which are recognized by the processing software. Template Markup Language leverages Lua programming language to provide a flexibility needed for the design of configurable IP cores.   CoreTML includes a Temlpate Markup Language processing tool, a graphical tool that can be used to configure the IP core, a couple of IP core examples and full documentation. CoreTML framework is licensed under the terms of the GNU Lesser General Public License (LGPL).   The development team also plans to develop a few more IP core examples to make a small configurable IP core library based on the CoreTML framework, as well as to make EDA integration smoother.   For more information please contact: Alex I. Kuznetsov Tel.: +7 916 8294445 (UTC+3) Email: ring0@ring0.co.cc Project website: http://coretml.sourceforge.net