tag 标签: scaling

相关博文
  • 热度 14
    2014-5-23 19:57
    1993 次阅读|
    0 个评论
    When trying to stretch the amount of energy one can get from a battery powering an MCU it’s important to remember, as I wrote last week, that we’re interested in current, not power , since battery capacity is measured in mAh. The equation for power has a hugely-seductive V squared term, but when we’re (correctly) thinking about current, voltage’s effects are linear. So, does it make sense to exploit current’s linear relationship with voltage? Consider the following graph for one of TI’s nifty MSP430 MCUs:   The curves above show a substantial reduction in current as the Vdd decreases. Even at 1 MHz, where the graph isn’t very dramatic-looking, there’s about a 2X improvement by scaling back the MCU’s supply voltage. So this sure looks like a great place to cut coulombs. It’s tempting to put in a low-dropout regulator to reduce Vdd to 2.0, but I can’t find any linear devices whose idle current during the MCU’s long sleep states won’t deplete the battery. Smarter parts can work, like TI’s $0.80 TPS 62736 buck/boost converter that needs only 400 nA for Iq. It does require an inductor, but those are only about 7 cents in quantity. Touchstone’s TS3310 has even better specs, but that company sold all of its assets to Silicon Labs recently; hopefully the latter company will continue to produce the product. But long-lived systems are almost always asleep. A device that has to run for a decade off a coin cell will be snoozing well over 99% of the time. The graph above is active current; cut that by half, and factor in the 1% or less awake time, and it’s clear that there’s really no benefit to scaling Vdd. What about cutting Vdd during the 99% of the time when the processor is sleeping? Most MCUs offer a number of sleep modes that each have differing energy needs. Some show a very small difference in worst-case consumptions; it’s common to find in a deep sleep only a 20% variation between 3 and 2 volts. 20% may be enough to justify an extra dollar’s worth of buck/boost parts as that could add a couple of years to the operating life of a very-low-power system. But remember that a ten-year life means the system’s average draw from a CR2032 can’t exceed 2.5 uA. The TPS 62736 will eat 400 nA of that budget. One vendor shows curves for “typical” sleep needs, and there’s about a 2X difference between 3 and 2 volts, which sounds promising. But under 3V the curve is labeled “limited accuracy.” I wrote about how little a “typical” spec means last August. Combine the meaninglessness of “typical” numbers with “limited accuracy” and I, for one, have no idea how to interpret the data. One wonders if the datasheet was created by marketing folks rather than engineers. “Take it from us, in some modes, it’s possible, based on a statistically meaningless set of observations, that the part might, if coupled to the wings of angels, work in your application.” Unfortunately, most datasheets don’t spec out the difference in sleep current as a function of voltage, so it’s impossible to know what benefits, if any, accrue from voltage scaling. As always, read the datasheets carefully and do a full analysis of your design goals.
相关资源
  • 所需E币: 1
    时间: 2022-7-23 18:16
    大小: 1.97KB
    上传者: Argent
    ScalinginCJ1CS1PLC
  • 所需E币: 3
    时间: 2019-12-24 22:52
    大小: 80.02KB
    上传者: 978461154_qq
    摘要:本设计指南中,电路采用10位ADC、电阻分压器以及外部基准,能够将ADC的实际精度提高至13位。本文展示了通过电压缩放,将10位ADC扩展至13位设计实例。文中分别描述了MAX15910位ADC、MAX5420电阻分压器以及MAX6141电压基准的特性。通过调整基准电压提高ADC精度FrancoContadiniMar04,2012摘要:本设计指南中,电路采用10位ADC、电阻分压器以及外部基准,能够将ADC的实际精度提高至13位。本文展示了通过电压缩放,将10位ADC扩展至13位设计实例。文中分别描述了MAX15910位ADC、MAX5420电阻分压器以及MAX6141电压基准的特性。为了提高灵活性,数据采集板应适合不同的输入电压范围,利用同一采集电路处理低幅度信号时往往需要增加几位分辨率,从而提高了系统成本。利用本应用笔记给出的简单电路,可以采用低成本10位ADC将实际精度提高至13位。图1ADC的1个LSB(最低有效位)为FSR/2n,其中n表示位数。FSR(满量程)取决于电压基准幅度。采用外部基准的MAX159是低功耗、108ksps串行ADC,封装于MAX-8,其输入范围为0至VDD+50mV。较宽的输入范围允许利用基准缩放技术来适应不同的输入范围。低成本、3端电压基准的输出通过数字可编程电阻分压器(MAX5420)进行缩放调节,分压器可提供精确的分压比(1、2、4、8)。分压比精度为0.025%至0.5%,取决于所选择的器件等级(A、B、C)。分压比由数字输入D1和D0决定,具体如下:表1.DIGITALINPUTSD1D0DIVIDERRATIO0010121……
  • 所需E币: 3
    时间: 2019-12-24 22:49
    大小: 80.02KB
    上传者: quw431979_163.com
    摘要:本设计指南中,电路采用10位ADC、电阻分压器以及外部基准,能够将ADC的实际精度提高至13位。本文展示了通过电压缩放,将10位ADC扩展至13位设计实例。文中分别描述了MAX15910位ADC、MAX5420电阻分压器以及MAX6141电压基准的特性。通过调整基准电压提高ADC精度FrancoContadiniMar04,2012摘要:本设计指南中,电路采用10位ADC、电阻分压器以及外部基准,能够将ADC的实际精度提高至13位。本文展示了通过电压缩放,将10位ADC扩展至13位设计实例。文中分别描述了MAX15910位ADC、MAX5420电阻分压器以及MAX6141电压基准的特性。为了提高灵活性,数据采集板应适合不同的输入电压范围,利用同一采集电路处理低幅度信号时往往需要增加几位分辨率,从而提高了系统成本。利用本应用笔记给出的简单电路,可以采用低成本10位ADC将实际精度提高至13位。图1ADC的1个LSB(最低有效位)为FSR/2n,其中n表示位数。FSR(满量程)取决于电压基准幅度。采用外部基准的MAX159是低功耗、108ksps串行ADC,封装于MAX-8,其输入范围为0至VDD+50mV。较宽的输入范围允许利用基准缩放技术来适应不同的输入范围。低成本、3端电压基准的输出通过数字可编程电阻分压器(MAX5420)进行缩放调节,分压器可提供精确的分压比(1、2、4、8)。分压比精度为0.025%至0.5%,取决于所选择的器件等级(A、B、C)。分压比由数字输入D1和D0决定,具体如下:表1.DIGITALINPUTSD1D0DIVIDERRATIO0010121……
  • 所需E币: 3
    时间: 2020-1-14 09:30
    大小: 3.6MB
    上传者: 238112554_qq
    DeviceStructuresandMaterialsforScalingtoSiLimitsandBeyondDeviceStructuresandMaterialsforScalingtoSiLimitsandBeyondKrishnaSaraswatMaterialsStructuresandDevicesMARCOFocusResearchCenter1FocusResearchCenterProgram:TimeScaleEssentialcomplementtoongoing,neartermeffortsFocuswhereevolutionaryR&DmaynotfindsolutionsTechnologyscaling0.13m200290nm200465nm200645nm200830-20nm201010nm?2012+currentnear-termR&D...MARCOFRCPAgenda2TheFourCurrentFocusCentersDesignandTestFocusCenterDirector:JanRabaey,BerkeleyComponent-baseddesign,constructivefabrics,fullyprogrammablesystems,test,verification,energy&power,calibratingachievabledesignsLeadSchool:U.C.BerkeleyCMUMITPennStatePrincetonPurdueStanfordUCLAUC……