标签: timing

玩转 Vivado 之 Timing Constraints 特权同学，版权所有          最近在熟悉 Xilinx 已经推出好几年的 Vivado ，虽然特权同学之前已经着手玩过这个新开发工具，但只是简单的玩玩，没有深入，这回得以静下心做些研究，并且纯粹是在 Vivado 软件的使用方面。最大的感受是，虽然大的框架，基本的流程和方法论上没有任何大的变化，不过“换汤不换药”。但是，在工具使用的一些细节上，即用户体验，尤其是易用性方面，能感受到 Xilinx 下功夫了。          这里就先拿 Timing Contrasint 方面来做点文章吧。首先是 Constraints Wizard ，这里一步一步往下走，几乎所有的 Constraint 遍历一次，对于第一次做 Constraint 非常方便。 图 1 Constraints Wizard 开启按钮          对于 Constraints Wizard 中 input/output 端口的约束，过去特权同学一到具体给定约束值时，老是范糊涂，因为 Quartus II 和 ISE 对 IO 端口的约束方式和计算公式略有不同，容易混淆。而老掉牙的 ISE 中也只是光秃秃的没有任何提示， Vivado 可好了，出现了标好了具体约束值的时序图，一目了然，很容易就可以下手做约束了。 图 2 Constraints Wizard 的 output 约束界面 图 3 ISE 中光秃秃的 Constraint 界面          另外一点， Xilinx 一直做得比 Altera 的 TimeQuest 好的是，对于 IO 端口约束过的和没有约束过的，都能够一目了然的分别列出来，让设计者不至于遗漏。 图 5 Constraints Wizard 的 output 约束界面          当然了，除了 Constraints Wizard ，还是有专门的 Timing Constraints 页面可以查看、编辑所有的约束。与以前的 UCF 文件不一样的是， Vivado 用新的格式 XDC 用于存储约束脚本。 图 6 Timing Constraints 页面          另外，特权同学还发现了一个非常好的功能，即约束模版（ Language Templates ）中的 XDC 模版。 图 7 Language Templates 开启按钮          Language Templates 中， ISE 也有时序约束的模版，但是比较下来，发现 Vivado 中增加了很多实用的模型，比如图 8 所示的 Center-Aligned -- Single Data Rate(SDR) ，里面有时序示意图，非常简单清晰，对于这类常用接口不需要再去研究 input/output 端口时序约束公式了，直接上来就可以填时间，然后 copy 到工程的 XDC 文件中。 图 8 Language Templates 页面          再说 XDC 文件的管理，它其实不光可以存储时序约束脚本，所有相关的设计约束脚本都是存储在 XDC 格式的文件中。而且可以有多个 XDC 文件同时存在一个工程中，它们可以 Enable 也可以 Disable 。对于一个难于收敛的时序设计，这个 Enable 和 Disable 功能就非常实用了。设计者通常会使用不同的约束策略，过去只能在一个文件里面改来改去，注释来注释去，极易混淆，但是这种多文件管理的支持，就非常便于管理和维护。          对于同一个工程，甚至可以同时查看不同约束策略下的时序报告，可以非常直观的对比。这一点在过去的 ISE 上咱没有试过，不知道可不可以，但是在 Quartus II 的 TimeQuest 中肯定不能，所以，这绝对又是一个亮点。  

I have recently finished reading the book Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) . It is written by Sridhar Gangadharan of Atrenta and Sanjay Churiwala of Xilinx. They also had help from Frederic Revenu, who wrote a chapter on the Xilinx extensions to SDC. Before I go any further I have to admit that I have never written a design constraint in my life, so I came at this book as someone who understood the problem but had never been involved with solving it. Back when I was doing design, we hardly even used a simulator let alone half of the tools that are available today. The book is very well structured and reads easily. Each chapter takes on a subject and develops it well. Even though I have never written constraints, I was able to follow along at each step, and the small examples they provided were helpful to me in understanding the lessons. The book is also completely tool-generic. The authors make no attempt to sell you on any particular tool, and you could read the book and not know that it came from an EDA company. If I have one complaint about this book: A chapter is missing. At several points in the book, the authors discuss how certain constraints are estimated or that information is not available until a certain point in the flow. They also explain how static timing can be useful at certain points in the flow for ascertaining different types of timing checks. While I understand that every company uses different tools and flows, I would have liked to see a chapter that explained the writing and evolution of constraints during the design process. What things should companies focus on at certain points in the flow? When should the constraints be updated? When should static timing be run? What useful information will it provide? This could have also included a larger, more typical example, and while I understand that the constraints files can become very large, it would have been helpful to look at something a designer may face. The actual constraints files could have been made available online and small parts of it described in the chapter. These comments, however, do not detract from the book. I highly recommend this book to anyone who needs to get acquainted with timing constraints. I feel that I could start writing them myself after reading this book. A content list is provided below: 1. Introduction 2. Synthesis Basics 3. Timing Analysis and Constraints 4. SDC Extensions through TCL 5. Clocks 6. Generated Clocks 7. Clock Groups 8. Other Clock Characteristics 9. Port Delays 10. Completing Port Constraints 11. False Paths 12. Multi-Cycle Paths 13. Combinational Paths 14. Modal Analysis 15. Managing your Constraints 16. Miscellaneous SDC Commands 17. XDC: Xilinx Extensions to SDC At 253 pages, the book lists at $119. More information can be found on the Springer site and the book is available slightly cheaper on Amazon . I would love to hear other people's opinions of this book, especially from those who have written design constraints in the past. Brian Bailey EE Times  

http://blog.sina.com.cn/s/blog_5f01ba3301010d3l.html     http://www.eefocus.com/zhangjingbin/blog/10-10/197031_98b6a.html

Q1: Does the tool analyze the path crossing clock domain when timing analysis? Can I see the results in the timing reports? A1: It analyzes the cross-clock domain paths if the two clocks are derived clocks (DCM/PLL/MMCM etc) or related clocks. ==========

from http://forums.xilinx.com/t5/Timing-Analysis/Hold-time-can-be-negative-zero-and-positive-can-you-explain-it/m-p/101052 ============= The easy way to think of setup and hold is that there is a sampling window .  This window in time is defined by its starting time and ending time, and both of these are referenced to the clock edge.  However the starting time of the window, or setup time, is positive when before the clock edge, and the end of the window, or hold time is positive when after the clock edge.    Clock edge is defined as T_0 Start of window is:  T_0 - setup End of window is T_0 + hold Note that setup and hold can both be negative, positive or zero .  i.e.  the sampling window can come entirely before the clock edge (positive setup, negative hold), it can start before and end after the clock edge (positive setup and positive hold), or it can come entirely after the clock edge (negative setup and positive hold). The important thing is that the sampling window should come while the input data is stable.  If the data changes during the sampling window, there is a timing error.