原创 xilinx setup and hold time

from http://forums.xilinx.com/t5/Timing-Analysis/Hold-time-can-be-negative-zero-and-positive-can-you-explain-it/m-p/101052

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The easy way to think of setup and hold is that there is a sampling window.  This window in time is defined by its starting time and ending time, and both of these are referenced to the clock edge.  However the starting time of the window, or setup time, is positive when before the clock edge, and the end of the window, or hold time is positive when after the clock edge.   

Clock edge is defined as T_0

Start of window is:  T_0 - setup

End of window is T_0 + hold

Note that setup and hold can both be negative, positive or zero.  i.e.  the sampling window can come entirely before the clock edge (positive setup, negative hold), it can start before and end after the clock edge (positive setup and positive hold), or it can come entirely after the clock edge (negative setup and positive hold).

The important thing is that the sampling window should come while the input data is stable.  If the data changes during the sampling window, there is a timing error.