原创 PlanAhead teminology

======UI==========

cell:
a functional unit, including IBUFG/BUFG primitive

instance:
an instantiation of cell

signal:
a normal signal

global clock:
a global clock signal

I/O site:
This is the physical package pin. It may or may not be used in your particular design. For example, E15 on the FF676 package for a Virtex-5 is an I/O site. 

I/O port:
This is the logical port on the design. It may or may not have a package pin(I/O site) that it is constrained to. For example, my clock named clk_100 is a port in my HDL. It is an I/O port on my design and could be constrained to I/O site E15, but doesn't have to be. 

Net:
This is the net between any source and load. For example, my design has a net named clk_100 that is driven by the I/O port clk_100 and drives a BUFG.