原创 Xilinx PlanAHead 11.5 introduction

PlanAHead 11.5 replaces the current PACETM I/O pin planning tool and the previous ISE floorplanning tools.

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Some terms:

1. When Project Navigator invokes the PlanAhead environment, it is referred to as ISE Integration mode.

2. A full featured standalone version of the PlanAhead design and analysis environment is also installed as part of ISE and can be called independently of Projnav/standalone mode .

If you wish to explore PlanAhead as a full featured tool, refer to the PlanAhead User Guide or PlanAhead Tutorial.

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ISE Integration mode Overview:

1. no inter-tool process communication.

DO NOT attempt to edit logic or constraints simultaneously in both tools.

2. A temporary PlanAhead project is created in the ISE project directory.

3. Only enables physical constraint modification for I/O pins, logic LOC and AREA_GROUP constraints.

4. Features that enable logic or timing constraint modification
have been disabled.

5. The only file(s) being passed back to Project Navigator are UCF constraint files.

6. Integrated Processes:

• I/O Pin Planning (Pre-Synthesis)

• I/O Pin Planning (Post-Synthesis)

• Floorplan Area/IO/Logic (Post Synthesis)

• Analyze Timing/Floorplan Design (Post Implementation)

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I/O Pin Planning :

use Post-Synthesis rather than Pre-Synthesis.

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Design Analysis and Floorplanning :

1. Area Groups (Pblocks) or Locations Constraints (LOC) can be easily be created.

2. Assign logic to specific CLBs or BEL level constraints to lock logic to specific gates within CLB sites (BEL & LOC) using Site based placement constraints (LOC).

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Timing Analysis and Floorplanning :

1. analyze placement and timing results, apply floorplanning techniques to improve design performance or runtimes.

2.
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Known Issues

1. I/O ports may not be passed successfully in the Pre-Synthesis process.

Workarounds:

• PlanAhead could be used in standalone mode to assign I/Os. The exported UCF file could then be used as a source file for the Project Navigator project.

• The Post-Synthesis process step should pass IO ports successfully.