原创 Xilinx Constraints Terminology

I myself have been trapped by these similar terminology for a while. Here's for others' reference and my contemplation.

general:

Primitive and macro -- http://forums.xilinx.com/t5/Virtex-Family-FPGAs/about-the-difference-between-macro-and-primitive-in-xilinx/m-p/6161

Component is the common name of all kinds of parts in a design. Usually, component is divided into element, something simple, and instance/submodle, something a bit complex.

Instance is usu. the common name of instantiation of primitive and macro.

Element is usu. used with component so as not to use one word two times, but sometime means simpler component, such as FF, IBUF and etc..

Symbol is usu. used with other central words, such as primitive, pad, macro and etc., for habitual usage.

Pad is physical port of top design, directly connect to die pin

Pin is design port of submodule/instance

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group constraint:

time group
containing many nets

input pad time group
time group containing input pad nets

input [clock/data] pad net
input [clock/data] net attached to the pad

PIN
port of submodule/instance

NET
port of top design or net within design, net connectivity

INST
instance of design