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【应用手册】AN584:TimingClosureMethodologyforAdvancedFPGADesignsToday’sdesignapplicationandperformancerequirementsaremorechallengingduetoincreasedcomplexity.Withtheevolutionofsystem-on-a-chipdesigns,designshavegrownlarger.Additionally,externalmemoryinterfacesandmixedsignaldevicesbringagreaterchallengetotimingclosure.Ifyouusethird-partyIPinyourdesigns,youmaynothavecontroloverhowtheseIPblocksarepipelined,orhowtheyarepartitioned.YourdesignmustaccommodatetimingrequirementsfortheIPusedinthesystemtoachieveafullyfunctionaldesign.Whenperformancerequirementsforanypartofadesignarenotcompletelymet,thesystemfailstofunctionasdesired.Thisapplicationnotefocusesonagenericmethodologyfortimingclosure.WhetheryouuseApplicationSpecificStandardProducts(ASSPs),ApplicationSpecificIntegratedCircuits(ASICs),orFieldProgrammableGateArrays(FPGAs),timingclosureposesachallengeforsystemdesign.TheQuartus®IIFitterdefaultsettingscanhelpyoumeetrequiredtimingconstraintsformostdesigns.However,forsomedesignsthatcannotmeettimingrequirementswithdefaultsettings,followthemethodologyinthisapplicationnotetoachievetimingclosurerequirements.Furthermore,theguidelinesandmethodologypresentedinthisdocumentcanhelpimproveproductivity,closetimingforyourdesignfaster,andreducethenumberofiterations.AN584:TimingClosureMethodologyforAdvancedFPGADesignsAugust2009AN-584-1.0IntroductionToday’sdesignapplicationandperformancerequirementsaremorechallengingduetoincreasedcomplexity.Withtheevolutionofsystem-on-a-chipdesigns,designshavegrownlarger.Additionally,externalmemoryinterfacesandmixedsignaldevicesbringagreaterchallengetotimingclosure.Ifyouusethird-partyIPinyourdesigns,youmaynothavecont……