【应用手册】AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs This application note covers topics from a timing closure perspective, for the successful migration to HardCopy® ASICs from Altera’s FPGAs. The first section covers metastability, synchronous and asynchronous resets, and synchronizing an asynchronous reset. This section also describes techniques for passing control and data signals across clock domains using a handshake mechanism and FIFO. The next section covers the concept of timing requirements at the system level (I/O constraints) and describes in detail what you must do to fully and properly constrain your design (I/O and internal timing constraints). This section focuses on timing constraints by introducing a few basic commands available in the TimeQuest Timing Analyzer that are the most critical for any design. This section also describes how you can properly constrain your design using Altera’s TimeQuest Timing Analyzer available in the Quartus® II software. AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs July 2010 AN-545-2.1 This application note covers topics from a timing closure perspective, for the successful migration to HardCopy ASICs from Altera’s FPGAs. The first section covers metastability, synchronous and asynchronous resets, and synchronizing an asynchronous reset. This section also describes techniques for passing control and data signals across c……