tag 标签: ASIC

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  • 热度 1
    2014-11-12 17:16
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    In this blog, I thought we should consider things in the context of microprocessors. In almost every piece of electronic equipment we use today, there will be some kind of microprocessor (MPU) or microcontroller (MCU) controlling the operation. Following Moore's Law, microprocessors have doubled in size every second year. When Intel introduced the 4004 microprocessor in 1971, it had about 2,300 transistors. By comparison, the latest Intel 64bit microprocessors contain more than 2.5 billion transistors.   This retrospective blog describes how I became involved in testing microprocessors in 1976, and how microprocessors have influenced my professional work for many years. Testing microprocessors A visit to the Computer History Museum's website will help us get a feeling for the evolution of the microprocessor. After working for a few years maintaining the computer-controlled test equipment at Ericsson, I realised it would be much more fun to program these beasts. I applied for a job with the microcircuit group in Ericsson's component test department. I got the job, and the first thing I had to do was to write a test program for the Motorola 6801 microcomputer. The 6800 was an eight-bit microprocessor designed and manufactured by Motorola. The MC6800 microprocessor was part of the M6800 Microcomputer System, which also included serial and parallel interface ICs, RAM, ROM, and a variety of other support chips. A significant design feature was that the M6800 family of ICs required only a single five-volt power supply at a time when most other microprocessors required three voltages. The M6800 Microcomputer System was announced in March 1974 and was in full production by the end of that year.   The MC6801 was a single-chip microcomputer based on a 6800 CPU with 128B of RAM, a 2KB ROM, a 16bit timer, 31 programmable parallel I/O lines, and a serial port. It could also use the I/O lines as data and address buses to connect to standard M6800 peripherals. The 6801 would execute 6800 code, but it had 10 additional instructions, and the execution time of key instructions was reduced. The two eight-bit accumulators could act as a single 16bit accumulator for double-precision addition, subtraction, and multiplication. This device was initially designed for automotive use, with General Motors as the lead customer. The first application was a trip computer for the 1978 Cadillac Seville. This 35,000 transistor chip was too expensive for wide-scale adoption in automobiles, which resulted in the creation of a reduced-function MC6805 single-chip microcomputer. Writing test programs for the Tektronix S-3260 test system It was not easy to write a test program that would fully test the MC6801 microcomputer's functionality. Up to that time (1976), we had been writing test programs only for simple TTL devices in the 74 series. Our tester could store 1,024 test vectors, which was sufficient for testing simple counters and adders, but we knew that we would need much more memory for testing a microprocessor. Also, I had to come up with a completely new method for testing. The solution was to use the tester memory as program memory connected to the processor bus. We could then compile small assembly programs and let the processor execute these programs and send the results back to the tester. This method was successful, so I wrote a paper which I presented at a Tektronix users meeting in Germany in 1979. Moving to Switzerland Two of my favourite winter activities are skiing and skating. The mountains in Sweden cannot compare to the Alps, so I found myself traveling to Austria and Switzerland every winter for one week's skiing. That was all I could afford at the time, but I always dreamed about skiing a whole winter in the Alps. That's why I started thinking about moving to Switzerland. At the users meeting in Germany, I had met a guy working for a Swiss company (Landis Gyr) in Zug. It had the same kind of Tektronix test equipment, and it used Motorola microprocessors. The company needed someone that could help them write test programs and I was hired. In October 1979, I packed my things and moved to Switzerland.   The photo above was taken in Zermatt in 1981 and shows me in front of the famous Matterhorn. (You will note that, unlike in the pictures with my previous blogs, there are no bell bottom trousers to be seen.) Testing the Motorola MC68000 My first task at Landis Gyr was to write a test program for the 16bit Motorola MC68000 microprocessor. This was a huge device that was presented in a 64-pin dual-in-line package. This was before the introduction of surface mount devices (which would be used in later versions).   The 68000 grew out of the Motorola Advanced Computer System on Silicon (MACSS) project, which was begun in 1976 to develop an entirely new architecture without backward compatibility. This was to be a higher-power sibling complementing the eight-bit 6800 line, rather than a backward-compatible successor. In the end, the 68000 did retain a bus protocol compatibility mode for 6800 peripheral devices, and a version with an eight-bit data bus was produced. However, the designers mainly focused on the future, or forward compatibility, which gave the M68K platform a head start against later 32bit instruction set architectures. For instance, the CPU registers were 32 bits wide, though few self-contained structures in the processor itself operated on 32 bits at a time. The MACSS team drew heavily on the influence of minicomputer processor designs, such as the PDP-11 and VAX systems, which were similarly micro-coded. I used the same approach for writing the test program for the 68000 as I used for the 6801, and I came up with a similar test setup. This time I added an external memory in which I could store the program code executed by the microprocessor. To generate the test program ('programme' for plan), I had to write a cross assembler for the 68000. Yes, at that time you could still write your own cross assembler, but I don't think you would do this today. The test program development was described in a document I presented at a Tektronix users meeting in Philadelphia in 1984. Here's a hand-drawn block diagram showing the test setup.   Moving back to Sweden After a few years in Switzerland, I came to realise that skiing was not the only thing in life, and that I missed the long summer days in Sweden. I moved back to Sweden, returned to my old job at Ericsson, and continued to write test programs for more and more complex devices. In the mid-1980s, I came in contact with a new device called an application-specific integrated circuit (ASIC). The design department at Ericsson had just designed its first ASICs, and it was our job to test them.   I summarise my time as a component test engineer with the illustration above. After 15 years of testing components, it was time to move on to new challenges. Though I didn't know it at the time, I was soon to become an ASIC designer myself, and this will be the subject of a future retrospective. Sven Andersson is an independent ASIC/FPGA design consultant.  
  • 2014-6-26 12:35
    579 次阅读|
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    I usually get questions about the differences between various types of devices, such as ASICs, ASSPs, SoCs, and FPGAs. Is an SoC an ASIC, or vice versa, for example? What's the difference between an ASIC and an ASSP? And should a high-end FPGA be classed as a form of SoC?   There are several problems here, not the least that the technologies and terminologies have evolved over time. Keeping this in mind, the following is my highly simplified interpretation of where these terms came from and what they mean today.   ASICs Let's start with an application-specific integrated circuit (ASIC). As the name suggests, this is a device that is created with a specific purpose in mind. When most people hear the term ASIC, their "knee-jerk" reaction is to assume a digital device. In reality, any chip that is custom-made is an ASIC, irrespective of whether it is analog, digital, or a mix of both. For the purposes of these discussions, however, we shall assume a chip that is either wholly or predominantly digital in nature, with any analog and mixed-signal functions being along the lines of physical interfaces (PHYs) or phase-locked loops (PLLs).   ASICs are typically designed and used by a single company in a specific system. They are incredibly expensive, time-consuming, and resource-intensive to develop, but they do offer extremely high performance coupled with low power consumption.   ASSPs Application-specific standard parts (ASSPs) are designed and implemented in exactly the same way as ASICs. This is not surprising, because they are essentially the same thing. The only difference is that an ASSP is a more general-purpose device that is intended for use by multiple system design houses. For example, a standalone USB interface chip would be classed as an ASSP.   SoCs A System-on-Chip (SoC) is a silicon chip that contains one or more processor cores -- microprocessors (MPUs) and/or microcontrollers (MCUs) and/or digital signal processors (DSPs) -- along with on-chip memory, hardware accelerator functions, peripheral functions, and (potentially) all sorts of other "stuff." One way to look at this is that if an ASIC contains one or more processor cores then it's an SoC. Similarly, if an ASSP contains one or more processor cores then it's an SoC.     On this basis, we could view ASIC (and ASSP) as being the superset term because it embraces SoC, or we could regard the SoC as being the superset term because it includes everything in an ASIC (or ASSP) along with one or more processor cores. Are we having fun yet?   FPGAs ASICs, ASSPs, and SoCs offer high-performance and low power consumption, but any algorithms they contain -- apart from those that are executed in software on internal processor cores -- are “frozen in silicon.” And so we come to field-programmable gate arrays (FPGAs). The architecture of early FPGA devices was relatively simple -- just an array of programmable blocks linked by programmable interconnect.   The great thing about an FPGA is that we can configure its programmable fabric to implement any combination of digital functions we desire. Also, we can implement algorithms in a massively parallel fashion, which means we can perform a humongous amount of data processing very quickly and efficiently.   SoC-class FPGAs Over time, the capabilities (capacity and performance) of FPGAs increased dramatically. For example, a modern FPGA might contain thousands of adders, multipliers, and digital signal processing (DSP) functions; megabits of on-chip memory, large numbers of high-speed serial interconnect (SERDES) transceiver blocks, and a host of other functions.   The problem is that the field-programmable gate array (FPGA) moniker no longer reflects the capabilities and functionality of today's programmable devices. We really need to come up with some new terminology that embraces everything today's state-of-the-art tools and technologies are capable of doing.   Of particular relevance to our discussions here is the fact that today's FPGAs can contain one or more soft and/or hard core processors. On this basis, should we class this type of FPGA as being an SoC? Well, personally I have to say that SoC doesn’t work for me, because I equate the term "SoC" with a custom device created using ASIC technology.   Another alternative would be to call these devices Programmable SoCs, or PSoCs, but Cypress Semiconductor has already got the PSoC moniker locked down. The Cypress devices feature a hard microcontroller core augmented with some programmable analog and programmable digital fabric (the digital fabric is more CPLD than FPGA).   Altera used to call its versions of these devices -- the ones that combine hard MCU cores with programmable FPGA fabric -- SoC FPGAs, but they seem to have evolved to just calling them SoCs. Meanwhile, Xilinx calls its flavor of these devices "All Programmable SoCs."   Personally, I'm undecided as to what would be the best name. I think I'd prefer to use PSoC if the folks at Cypress hadn’t already taken control of this appellation, but they have, so we can't. Failing this, I guess I'd opt for SoC FPGA... unless you can suggest something better.
  • 2013-5-27 13:09
    4613 次阅读|
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      Dear Readers,   Here I would like to share some understanding on keyword called  "this" . What is  "this"  in System Verilog? How does it used? Usage of  "this"  is simple but important in test bench development.   First of all lets understand What is  "this"  in System Verilog?   "this"  is a key word in System Verilog used to unambiguously refer to class properties or methods of current object. The  "this"  keyword shall only used within a non-static class methods otherwise an error shall occur.   As example is the best way to understand the most of the things, let me take a example and try to explain. Example to understand the usage of  "this"  in System Verilog:   #############################################       class  ASICwithAnkit ;          int  a ;          function new  ( int  a);             this .a = a;          endfunction  : new       endclass  : ASICwithAnkit //Class instantiation and usage ASICwithAnkit  AwA =  new  (123); $display  ("AwA.a = %d,", AwA.a); ##########################################   In above example we can see that 'a' is a member of class "ASICwithAnkit". When we initialize the memory for class for usage, we have passed a integer value '123' to its constructor (function new). The variable 'a' is local to class instance "AwA and is now 123 as we have passed this from constructor.   Hope this is useful to understand the meaning and usage of  "this"  in System Verilog.   Happy Reading ! ASIC With Ankit
  • 热度 2
    2013-3-13 21:53
    1906 次阅读|
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    Dear Readers, I have been hearing on re-spins of chips. Many companies have gone through this painful phase because of several reason/defects. Nobody likes re-spin for chip as it is expensive and time consuming! Companies have a fear to loose time to market for their products because of this reason.   Let us understand the various factors which could cause re-spin for chips. If you ask industry experts or Semiconductor veterans they could share their experience. I have been discussing this topic with couple of people and have concluded few factors which could cause re-spin. Firmware Issues Power Issues Mixed-Signal Interface related Issues Race Condition Issues Clocking domain Issues Functional Issue etc... From the experience and discussion it looks like most of the time Function Issues/defects have triggered a re-spin for the Chips. When we talk about functional issues, attention comes to our mind is for functional logic verification part. Considering complexities in the ASICs companies have started investing time and money for the functional verification part of the Chips to reduce the chances of re-spin.   To reduce the chances of re-spin for chips, people have started using various precautions like   1. A reusable and scalable verification 2. More effective block (IP) level verification. 3. Verification reuse from block level to System level 4. Constraint Random Verification approach 5. Architecture of test bench using reusable methodologies Random functional verification is giving us a enough confidence on functional defects. Random verification generates corner scenarios, stress testing on functional scenarios and logical permutation for configuration.   Random verification just gives us a confidence on functional defects but not giving us confirmation that Chip will not have to go through re-spin because of any of the functional issue.   Share your experience on Chip re-spin.   Happy Reading-Sharing, ASIC With Ankit
  • 热度 1
    2013-2-10 01:08
    4742 次阅读|
    1 个评论
    As we all know the semiconductor market looks good now days and lots of companies are hiring talents for 2013-14 projection. If we keep this projection in mind, we could say there would be a business for the companies for upcoming years. Now, the billion dollar question: ‘ how about the resources ’? We have been observing from last few months that companies are struggling in finding good experienced/skilled resources. Usually product/service companies are playing with smart approach of having hierarchical engineering model where there are few junior/college graduates engineers working under guidance of one senior/Lead engineer. Approach looks smart and efficient to utilize resources appropriately and makes engineering execution cost effective too! At the same time executive and managers always thinks on cost effective and efficient engineering model to fulfill dynamic time to market! Many companies are working with different approach to utilize and manage engineering resources efficiently. There are cases or project specific critical requirements where you don’t have time to train your junior resources, in this type of requirement; you cannot take a chance of using junior level resource, if you do so, you might lose the schedule, budget and at the end market which is very important! There could be a requirement where you don’t need all your skilled resources to work on. For this type of requirement you can create a hierarchical approach of your engineering model to use the skillset efficiently. (This is where the engineering management comes in picture, Managers; Executives have to take efficient decisions to move forward in this type of situation otherwise in long go, you could see impact on quality and customer) Now a day, most requirements and needs from the product based companies are for senior engineers, considering the critical project requirement and quick execution to make the products ahead in the market. Companies are feeling shortage of skilled resources. At the same time people don’t move easily! Question here is; does this create shortage of experienced skillsets ? When market is in good shape, revenue and financial graph is growing mostly all the companies are in need of skilled man power and that’s where competition comes in picture for companies and engineers too! There can be different type of situations where market is not in good shape and companies are struggling to get the business. In these types of situation Smart companies usually starts investing in engineering man power to develop the skillsets keeping projection in mind, by the time skilled requirement comes, company already have skilled/trained resources ready to jump in to! There can be other type of situation where market might or might not be in good shape. Irrespective of market Situations Company sometime announces on ‘ restructuring the engineering force ’ which means company directly or indirectly fires engineers as a part re-structuring. Mostly this situation comes because of shortage of business for company (particular business division of company). These types of situations are still debatable and require dynamic changes based on the market, need, requirements etc…  But still the question remains same at any point of time ‘ Are Companies Running Short Of Business or Short Of Resource? ’    Thanks, Ankit Gopani (ASIC With Ankit)
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    用多片FPGA进行ASIC设计验证的分区和综合技术用多片FPGA进行ASIC设计验证的分区和综合技术本文将介绍,如何在专业的验证软件Certify的帮助下,实现快速有效的用多片FPGA来进行ASIC设计验证。前言在现在复杂的ASIC设计中,校验(Verification)是最大的瓶颈。随着先进的半导体工艺技术不断前进,随之带来的是ASIC设计规模和设计复杂度的飞速增长,这使得传统的软件仿真工具已经无法完全解决验证的问题。而且随着越来越多的需要处理大量实时数据的应用(如视频)出现,验证技术就要求能够在接近实时频率的条件下进行验证。现在越来越多的ASIC设计者自己设计FPGA验证板来进行ASIC设计验证。用FPGA验证ASIC的好处是可以使软件的开发调试和ASIC的开发调试并行的进行。ASIC的设计者在用FPGA做验证和调试的时候会面临很多挑战。一个最大的问题就是即使是:最大容量的FPGA和复杂的ASIC相比还是太小。这意味着设计者必须把他们的ASIC设计分割到几块FPGA中。在作分割和FPGA综合的时候,没有工具帮他们做出好的分割决定,也很难确定验证板的参数和设计。这样设计者只能单调乏味的在分割、综合、板上实现几个步骤中重复,浪费大量的时间。Certify是SYNPLICITY公司的新一代设计软件,它就是针对用FPGA做ASIC验证的设计。Certify结合了RTL多片分割和业界最好FPGA综合技术。它是业界的第一个也是唯一一个针对使用多片FPGA做ASIC验证的设计工具。SOC(片上系统)ASIC的验证方法ASIC设计者面临着一系列的压力。他们的设计要达到最高的集成度,并且……
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    我们已使用PXIExpress自动测试系统完成多个项目,并获得非常满意的效果。自动测试系统大大减少了芯片测试的时间,而其快速、准确的直流测试更是实验室的宝贵财富。使用PXI模块化仪器完成超低功耗ASIC设计的结构和内存测试"我们已使用PXIExpress自动测试系统完成多个项目,并获得非常满意的效果。自动测试系统大大减少了芯片测试的时间,而其快速、准确的直流测试更是实验室的宝贵财富。"-MarioKonijnenburg,HolstCentre/imecTheChallenge:创建灵活的测试系统用于自动验证和表征新的超低功耗半导体芯片设计。TheSolution:使用NILabVIEW软件和NIPXIExpress高速数字I/O设备开发自动测试系统,前者读取测试向量,后者产生和接收数字数……
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