【应用手册】AN 584: Timing Closure Methodology for Advanced FPGA Designs Today’s design application and performance requirements are more challenging due to increased complexity. With the evolution of system-on-a-chip designs, designs have grown larger. Additionally, external memory interfaces and mixed signal devices bring a greater challenge to timing closure. If you use third-party IP in your designs, you may not have control over how these IP blocks are pipelined, or how they are partitioned. Your design must accommodate timing requirements for the IP used in the system to achieve a fully functional design. When performance requirements for any part of a design are not completely met, the system fails to function as desired. This application note focuses on a generic methodology for timing closure. Whether you use Application Specific Standard Products (ASSPs), Application Specific Integrated Circuits (ASICs), or Field Programmable Gate Arrays (FPGAs), timing closure poses a challenge for system design. The Quartus® II Fitter default settings can help you meet required timing constraints for most designs. However, for some designs that cannot meet timing requirements with default settings, follow the methodology in this application note to achieve timing closure requirements. Furthermore, the guidelines and methodology presented in this document can help improve productivity, close timing for your design faster, and reduce the number of iterations. AN 584: Timing Closure Methodology for Advanced FPGA Designs August 2009 AN-584-1.0 Introduction Today’s design application and performance requirements are more challenging due to increased complexity. With the evolution of system-on-a-chip designs, designs have grown larger. Additionally, external memory interfaces and mixed signal devices bring a greater challenge to timing closure. If you use third-party IP in your designs, you may not have cont……