原创 5人表决器

2009-8-25 08:37 2819 9 9 分类: FPGA/CPLD

module vote(fiveman,out,clk,rst_n);
input clk;
input rst_n;
input[4:0] fiveman;
output out;


reg[4:0] fiveman_r;
reg [2:0] count;
reg out_r;
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin
   count <= 0;
   out_r <= 0;
   fiveman_r <= 0;
   end
else   begin
 fiveman_r = fiveman;
 count = 0;
 while(fiveman_r)
  begin
  if (fiveman_r[0] ) count = count +1'b1;
  fiveman_r = fiveman_r>>1;
  if (count>2) out_r = 1;
  else out_r = 0;
  end


 end
  


assign out = out_r;
endmodule


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