原创 分频器

module frequency(fre_count ,f,out,clk,rst_n);
input clk,rst_n;
input f;   // 进来的频率
input [4:0]fre_count;   //分频的倍数
output out ;            // 分频后的输出

//---------------------------------------------------------
reg f0,f1,f2;        //f信号寄存器，捕捉下降沿滤波用
wire neg_f;         // f下降沿标志位

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   f0 <= 1'b0;
   f1 <= 1'b0;
   f2 <= 1'b0;
  end
 else begin
   f0 <= f;
   f1 <= f0;
   f2 <= f1;
  end

assign neg_f =  ~f1 & f2; //捕捉到下降沿后，neg_f拉高保持一个主时钟周期
//-----------------------------------------------------------
reg[4:0] count;
reg[4:0] freCount_r;
reg out_r;
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
  count <= 0;
  freCount_r <= 0;
  out_r <= 0;
  end
else  begin
  freCount_r = fre_count;
 if (neg_f) count = count+1'b1;    //测频
 if (freCount_r == count) begin    // 分频
    count = 0;
    out_r = ~out_r;
    end

 end
assign out = out_r; 
endmodule
//---------------------------------------------------------

https://static.assets-stash.eet-china.com/album/old-resources/2009/8/25/50cab70f-e07b-462e-a4fd-577638837c4d.rar  frequency.vwf