原创 Performing Design Exploration

2008-10-21 10:40 2960 6 6 分类: FPGA/CPLD
Copy from: DC user guide, Chapter 9 Optimizing the Design.

Performing Design Exploration


In design exploration, you use the default synthesis algorithm to
gauge the design performance against your goals. To invoke the
default synthesis algorithm, use the compile command with
no options:

dc_shell-xg-t> compile

The default compile uses the -map_effort medium option of the
compile command. The default area effort of the area recovery
phase of the compile is the specified value of the map_effort
option. You can change the area effort by using the -area_effort
option.

If the performance violates the timing goals by more than 15 percent,
you should consider whether to refine the design budget or modify
the HDL code.

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