原创 About set_clock_uncertainty

Comes from: http://www.edacn.net/bbs

Synthesis:

set_clock_uncertainty -setup = jitter+skew(+margin)

set_clock_uncertainty -hold   = skew(+margin)



pre-layout STA:

set_clock_uncertainty -setup = jitter+skew(+margin)

set_clock_uncertainty -hold   = skew(+margin)



P&R:

set_clock_uncertainty -setup = jitter(+margin)

set_clock_uncertainty -hold   =(margin)



post-layout STA:

set_clock_uncertainty -setup = jitter(+margin)

set_clock_uncertainty -hold   =(margin)

Margin is related to process technology. Generally, foundry factory has the recommented value.

Uncertainty comes from the PLL jitter, clock frequency, clock skew, clock source uncertainty.
Usually, PLL jitter is defined in PLL databook.