原创 About set_clock_uncertainty

2009-3-13 18:23 4245 8 8 分类: FPGA/CPLD
Comes from: http://www.edacn.net/bbs

Synthesis:

set_clock_uncertainty -setup = jitter+skew(+margin)

set_clock_uncertainty -hold   = skew(+margin)



pre-layout STA:

set_clock_uncertainty -setup = jitter+skew(+margin)

set_clock_uncertainty -hold   = skew(+margin)



P&R:

set_clock_uncertainty -setup = jitter(+margin)

set_clock_uncertainty -hold   =(margin)



post-layout STA:

set_clock_uncertainty -setup = jitter(+margin)

set_clock_uncertainty -hold   =(margin)

Margin is related to process technology. Generally, foundry factory has the recommented value.

Uncertainty comes from the PLL jitter, clock frequency, clock skew, clock source uncertainty.
Usually, PLL jitter is defined in PLL databook.

文章评论0条评论)

登录后参与讨论
EE直播间
更多
我要评论
0
8
关闭 站长推荐上一条 /6 下一条